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The prevalence of bridging defects makes bridging fault models important to consider during fault simulation and test generation. The large number of bridging faults that can be defined for a circuit led to the development of procedures for selecting subsets of bridging faults that are likely to occur based on the circuit layout, and hard-to-detect bridging faults whose coverage provides a more effective...
In this work, a simple electric circuit model for the evaluation of the impact of vias (inter-metallic vertical connections) in resonant rotary traveling wave oscillator (RTWO) is proposed. A test structure was designed to quantify the degradation on the signal integrity of RTWOs caused by these vias. The test structure and the RTWO were designed according to the rules of the 130 nm commercial mixed...
This paper presents a hybrid approach to the investigation of the performance of printed circuit boards (PCB) by examining the impact of parasitic parameters of the board design on the efficiency of a device. First, parasitic parameters are extracted from the board layout by 3D quasistatic field solvers. Second, the corresponding equivalent circuit is constructed. Third, the extracted parasitic circuits...
Gate-all-around nanowire transistor is deemed as one of the most promising solutions that enables continued CMOS scaling. Compared with FinFET, it further suppresses short-channel effects by providing superior electrostatic control over the channel. Due to the unique device structure, gate-all-around nanowire transistor also allows more efficient layout design by exploiting 3-dimensional stacking...
In this paper we investigate computer based methods for parasitic extraction in printed circuit board designs. We developed an automated flow for annotating functional designs without affecting design integrity.
Photon Emission Microscopy is the most widely used mainstream defect isolation technique in failure analysis labs. It is easy to perform and has a fast turnaround time for results. However, interpreting a photon emission micrograph to postulate the suspected defect site accurately is challenging when there are multiple abnormal hotspots and driving nets involved. This is commonly encountered in dynamic...
Ultra-scale devices based on technologies below 20nm are nowadays widely adopted due to their elevated computing features and low power consumption. These characteristics made them attractive even for fields where the high reliability is the major concern like automotive or aerospace ones. In order to guarantee a high reliability level, one of the major challenge in these application fields is the...
To tackle the key issues of monolithic heterogeneous integration, fast yet low power processing, high integration density, fast yet low power storage, the goal of the GREAT project is to co-integrate multiple functions like sensors (“Sensing”), RF receivers (“Communicating”) and logic/memory (“Processing/Storing”) together within CMOS by adapting the STT-MTJs (Magnetic devices) to a single baseline...
Use of computational electromagnetics (EM) in the design of radio-frequency integrated-circuit (RFIC) is presented. Computational EM is not only essential, but also inevitable, for RFIC design without it, it is simply not possible to accurately design (or even design) RFICs effectively and timely. Several examples including RFIC band-pass filter and power amplifier designed based on computational...
Power electronic applications need high voltage and current ranges which are impossible to obtain with discrete devices. Parallelization technique is a solution to increase power converter current capacity. Current distribution problems may reduce device lifetime and cause converter malfunction. Parallelization requires a total control of circuit parasitic elements which depend on layout physical...
Analog/Mixed-Signal (AMS) design and verification is dominated by modelling tasks. Model validity is crucial for the design's correctness but lacks a more formal criterion. We propose a novel model verification strategy to evaluate the coverage with respect to a given circuit. We define model-coverage based on the individual acceptance regions in parameter space. This imposes a measure that can be...
This paper presents layout-considerations for common-base amplifiers operating in the deep millimeter-wave region around 200 GHz. The effects of the parasitics for different layouts have been investigated, searching for the optimal performance in terms of gain and bandwidth of operation. Different layouts have been tested with the fabrication of two common-base amplifiers. The employed fabrication...
In this paper, the major methodologies proposed in the last years to speed-up the synthesis of radio-frequency integrated circuits blocks are overviewed. The challenges to automate this task are discussed, and, to avoid non-systematic iterations between circuit and layout design steps, the architecture of an innovative solution is proposed. The proposed tool exploits the full capabilities of most...
In contrast to other studies in IC supply chain security where foundries are classified as either untrusted or trusted, a more realistic threat model is that the foundries are legally and economically obliged to perform trustworthy service, and it is the individual employees that introduce security risks. We call the above as the trusted foundry and untrusted employee (TFUE) model. Based on this model,...
This paper proposes a free and complete EDA framework for teaching CMOS full-custom design of mixed-signal integrated circuits. The presented set of EDA tools and associated physical design kit should allow students to gain hands-on experience on schematic entry, both at system and circuit levels, HDL system simulation and block specification, automatic circuit optimization, PCell-based netlist-driven...
With the advance of the semiconductor technology power density and related thermal management issues became design bottlenecks. These physical limits require design engineers to make several thermal aware decisions during the design process: the earlier the better. Modern hardware description languages have extensions for simulation of mixed-signal circuits (e.g. SystemC-AMS, Verilog-AMS, VHDL-AMS)...
Previous work on the Carnegie Mellon Logic Characterization Vehicle (CM-LCV) has emphasized the diagnosability properties of a specific class of regular circuits called functional unit block arrays (FUB arrays). This paper describes a multiple-defect, two-level diagnosis procedure that leverages these unique properties of the FUB array to significantly improve diagnosis. This custom diagnosis procedure...
In today's diversified semiconductor supply-chain, protecting intellectual property (IP) and maintaining manufacturing integrity are important concerns. Circuit obfuscation techniques such as logic encryption and IC camouflaging can potentially defend against a majority of supply-chain threats such as stealthy malicious design modification, IP theft, overproduction, and cloning. Recently, a Boolean...
In this paper we present a tool, NANOcom, specifically developed for the bottom-up design and formalization of electronic circuits with a regular, matrix-like, structure. NANOcom allows to easily describe any kind of circuits and technologies where neighboring logic elements are dynamically coupled. Logic elements and interconnections are placed on a three-dimensional grid. Each element is characterized...
The stuck-at faults are basic faults that fail the chips. Various defects in the circuit can develop into stuck-at faults. To detect more defects caused by stuck-at faults, some of the fault sites may need to be detected multiple times. Thus, the existing pattern generation techniques provide N-detect ATPG, where each fault site would not be removed from the fault list before it is detected for N...
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