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As more and more distributed generations are connected to the grid, the features of micro grid, are no longer the same as conventional grids. A micro-grid fault diagnosis method based on redundant Petri net considering temporal constraints is put forward in this paper. Firstly, a tripartite criterion for fault location is proposed on basis of Wide-area information protection method. Secondly, The...
Vienna rectifier is one of the most popular topologies for three-phase PFC converter. Many control schemes were presented for Vienna rectifiers with unity power factor. Because of the small phase shift θ caused by the inductor or current detection delay, a zero-crossing detection error occurs, resulting in zero-crossing current spikes. This paper presents two SVPWM methods for three phase Vienna rectifiers...
Along with advances in modern VLSI technology, delay faults are becoming ever more important. On the other hand, the strength of SAT-solver engines has made them an attractive means for solving many Computer Aided Design (CAD) problems. This paper presents a new SAT-based Automatic Test Pattern Generation (ATPG) approach targeting transition delay faults using a novel 8-value encoding system. Experimental...
Three-dimensional range-finding systems are widely used in various applications and fields. Especially on mobile devices and automotive, the measurement stability and reliability are strongly required under a strong ambient light like a sunlight. The projected and reflected light is often much weaker than the strong background light. This paper presents a new 3-D Range-finding system which is based...
This paper shows the circuit level performance comparison of low-κ and high-κ spacer Junctionless FinFET(J-FinFET). TCAD simulations show that for high-κ (HfO2, κ=22) spacer J-FinFET, the device performance parameters such as DIBL (drain induced barrier lowering), SS (sub-threshold swing) and ION/IOFF improved by 14.5 %, 5% and 3.5x respectively as compared to low-κ (SiO2, κ=3.9) spacer J-FinFET....
Two hybrid memristor-MOS exclusive OR (XOR) and exclusive NOR (XNOR) logic gates based on Memristor Ratioed Logic (MRL) are presented. The proposed gates present logic states with voltages, and implement the logic operation within one clock cycle. The designs ease the voltage degradation problem of the original MRL logic gates, while consuming fewer area overhead and less delay than their counterparts.
Annotation — This paper presents a synthesis method for delay time evaluation in the printed circuit boards based on Timed Hard Petri Nets. For the specification and modeling of the delay time evaluation system, Timed Synchronous Petri Nets (TSPN) are used. The transition to the hardware description of the system is achieved by translating the TSPN into Timed Hard Petri Net (THPN). The implementation...
Excessive IR-drop during scan shift can cause localized IR-drop around clock buffers and introduce dynamic clock skew. Excessive clock skew at neighboring scan flip-flops results in hold or setup timing violations corrupting test stimuli or test responses during shifting. We introduce a new method to assess the risk of such test data corruption at each scan cycle and flip-flop. The most likely cases...
Process variation is increasing with each successive technology node, and it has reached the point where the worst-case timing modelling employed by current FPGA CAD tools is significantly underutilizing the available silicon. Previous studies have proposed exploiting FPGA reconfigurability to reduce this underutilization using techniques such as late binding and dynamic voltage scaling. Most of the...
Through Silicon Vias (TSVs) are crucial elements for the reliable operation and the yield of three dimensional integrated circuits (3D ICs). Resistive open defects are a serious concern in TSV structures. In this paper, a post-bond, parallel testing technique is proposed for the detection and location of resistive open defects in TSVs, which is based on easily synthesizable all digital testing circuitry...
In order to expand the class of control objects that require executing the complex regulation law, the author proposes a new method of organizing computing activities on the basis of the principle of non-use of the half-adder, the method implies the formation of all the digits of the result during one cycle of machine time. Mathematical models, which organize computations of methodically maximum speed,...
A switched-capacitor circuit is proposed for the generation of noise resembling the typical noise spectral density of MOS devices. The circuit is based on the combination of two chaotic maps, one generating 1/f noise (hopping map) and the other generating white noise (Bernoulli map). Through a programmable weighted adder stage, the contribution of each map can be controlled and, thereby, the position...
This paper proposes a novel circuit transformation based method to generate tests for cross-wire open, transistor stuck-open and delay faults inside CMOS cells/gates as well as transition faults in interconnects between gates using a unified model, called dynamic aggressor-victim type of bridging fault model (DBF). The unified fault model allows handling all these faults in one ATPG run and thus the...
Interconnect design has recently become one of the important factors that affect the circuit delay and performance especially in the deep submicron technology. The modelling of interconnects is typically based on using Elmore definitions of the delay time and rise time. So, a general formula for Elmore delay time and rise time in the fractional order domain are presented in this work. It is found...
In this paper, we present a simple analytical delay model for memristive memory cells. The output voltage evolution is obtained analyzing the charge-flux dynamics when a voltage ramp is applied to the input. From this evolution, the propagation delay is calculated. The model is validated using the VTEAM memristor model for different input rise time values of the applied ramp. The proposed model can...
Comparators are a critical element of Analog-to-Digital converters (ADCs) intended to operate in a harsh environments such as the automotive. The influence of temperature on key comparator properties such as the delay must be well understood to maximize their speed. In this paper a Double-Tail latch analysis leads to an analytical expression for the delay to more accurately guide the design over a...
From year to year there are lot of new requirements regarding to the lifetime and reliability of integrated circuits (IC) especially in automotive applications. In align with technology scaling the amount of device's reliability issues are increasing but the quality requirements becoming stronger. Now the aging phenomena becomes one of the critical issues in applications with longer life time. Hence...
Sub-threshold circuit is a promising circuit design style for IoT application, but the timing closure, especially hold timing fixing is a big challenge for designers. This paper proposes a mathematical method to estimate the number of insertion inverters/buffers for hold timing fixing in each short path. Firstly, the distribution of path delay is rigorously proved to be lognormal distribution in the...
Computing circuits suffer from the process, voltage and temperature variations and aging. These factors reduce yield and lifetime of the circuits and therefore limit the advance in modern computing technology. The process variations and aging result in timing failures that often can be resolved by delay matching. However, this strategy requires delay elements which cause additional power cost. We...
This paper proposes a topology optimization method for dual-threshold (DT) independent-gate (IG) FinFET circuits. In the proposed method, a node extraction algorithm is developed to extract the characteristic nodes of a BDD expression, which are suitable to be realized with the compact logic gates based on the DT IG FinFET devices, and then the equivalent replacement program that these extracted characteristic...
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