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Information diffusion models typically assume a discrete timeline in which an information token spreads in the network. Since users in real-world networks vary significantly in their intensity and periods of activity, our objective in this work is to answer: How to determine a temporal scale that best agrees with the observed information propagation within a network? A key limitation of existing approaches...
Adiabatic logic is an alternative architecture design style to reduce the power consumption of digital cores by using AC power supply instead of DC ones. The energy saving of the digital gates is strongly related to the efficiency of adiabatic AC power supplies. In this paper, we propose a resonant reversible power-clock supply design with four different phases. The resonance deviation between the...
More than eighty different test environments need to be created and maintained for debugging the Marvell Ethernet PHY chip if the traditional industrial verification methodology is being used. This can easily incite very complicated debugging procedures and cause the problems and concerns of a multitude of engineering resources. The latest Marvell Ethernet PHY IC UVM verification platform integrating...
In beyond silicon research, Quantum-dot Cellular Automata (QCA) emerged as a candidate for replacing the traditional CMOS logic circuits. QCA is a paradigm based on the exchange of information between cells that takes advantage of Coulomb's law. In this work, we managed to extract dependence relations through a circuit designed on QCA Designer simulator. We built small models representing fragments...
Annotation — This paper presents a synthesis method for delay time evaluation in the printed circuit boards based on Timed Hard Petri Nets. For the specification and modeling of the delay time evaluation system, Timed Synchronous Petri Nets (TSPN) are used. The transition to the hardware description of the system is achieved by translating the TSPN into Timed Hard Petri Net (THPN). The implementation...
Correlated double sampling(CDS) operation is generally used in CMOS imaging systems, implemented by switched capacitor(SC) circuits, to get rid of reset noise and decrease flicker noise. This paper presents an optimization method for the noise performance of a CDS circuit, the advantage of which is its ability of canceling the offset of the OP involved. The structure of the CDS circuit is analyzed...
As DSP is more and more widely used in the field of power electronics conversion, in order to enhance the comparability between the result of simulation and the experimental result of DSP control system, and increase the portability of the simulation program, it is very necessary to set up a fully digital power electronic simulation system based on imitating the working mechanism of DSP. This paper...
Excessive IR-drop during scan shift can cause localized IR-drop around clock buffers and introduce dynamic clock skew. Excessive clock skew at neighboring scan flip-flops results in hold or setup timing violations corrupting test stimuli or test responses during shifting. We introduce a new method to assess the risk of such test data corruption at each scan cycle and flip-flop. The most likely cases...
This paper describes a new methodology of construction of the internal activity block of an ICEM-CE model of an FPGA based on a predictive approach using the estimation tools of the dynamic power and the static timing proposed by the manufacturer of the integrated circuit.
In digital logic circuits, unconstrained scan tests are known to evoke much higher switching activity than functional modes. To create test conditions which are as similar as possible to functional modes, today's ATPG tools have knobs to constrain the switching activity of the generated test to a user-defined functional (= lower) level. Two-dimensional system chips (SoCs) and three-dimensional stacked...
Comparators are a critical element of Analog-to-Digital converters (ADCs) intended to operate in a harsh environments such as the automotive. The influence of temperature on key comparator properties such as the delay must be well understood to maximize their speed. In this paper a Double-Tail latch analysis leads to an analytical expression for the delay to more accurately guide the design over a...
Using a new DC offset compensation method, a fully differential track and hold circuit is presented. It stores an amplified version of the offset during the hold phase, which is used in attenuated fashion during the track phase to compensate offset. This scheme is less sensitive to charge injection and other errors than conventional offset compensation schemes. Experimental results of a test chip...
This work presents circuit design techniques for infield forming of metal-oxide memristor-based systems. While several works have addressed forming from a device characterization stand point, to the best of the authors' knowledge, the integration of a forming circuit in a memristor-based application hasn't been thoroughly studied. Two challenges exist for in-field forming which are the high forming...
In this paper, an X-tree clock distribution topology based on standing wave oscillator is introduced. To increase output amplitude at the loading point and saving chip area, a novel CMOS active inductor is designed and applied to each loading points of the network. The cascoded differential active inductor is 1 nH with Q = 344 at 10 GHz. This makes the two stage, 6.2 mm × 6.2 mm dimensional standing...
There is a growing interest among universities and industry in the field of nano, micro and cube Satellites. These are very small satellites, about the size of a shoebox, which can be launched into space at a much lower cost than typical large satellites. CubeSats are generally low earth orbit-LEO-satellites, which mean they orbit are from 200 to 1200 km above earth surface. Due to the small nature...
In this paper, we propose a logic-testing based HT detection and classification method utilizing steady state learning. We first observe that HTs are hidden while applying random test patterns in a short time but most of them can be activated in a very long-term random circuit operation. Hence it is very natural that we learn steady signal-transition states of every suspicious Trojan net in a netlist...
Ultra-deep sub-micron technologies are more vulnerable to different types of uncertainties. In this paper, we introduce a novel methodology to estimate the vulnerability of sequential circuits to soft errors at gate level. A new probabilistic modeling of SET propagation is proposed, which reduces the complexity of unrolling sequential circuits. This approach enables a multi-cycle error propagation...
In this paper we study the susceptibility of an integrated circuit, a Gigabit Ethernet Switch (GES), under Near Field Scan Immunity (NFSI) injection. The NFSI measure highlighted the weakness of the clock circuit of the GSE. The goal of this work is to model, simulate and predict such phenomenon. First, the model of the NFSI probe, based on 3D construction using CST™ studio Electromagnetic Software,...
Industrial Control Systems (ICS) are found in critical infrastructure such as for power generation and water treatment. When security requirements are incorporated into an ICS, one needs to test the additional code and devices added do improve the prevention and detection of cyber attacks. Conducting such tests in legacy systems is a challenge due to the high availability requirement. An approach...
This paper describes a new methodology of construction of the internal activity block of an ICEM-CE model of an FPGA based on a predictive approach using the estimation tools of the dynamic power and the static timing proposed by the manufacturer of the integrated circuit.
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