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In this work, a systematic analysis of the transmission line models used for high-frequency global interconnection lines is presented. As part of this analysis, two model implementations are carried out using: i) the technology parameters provided by the manufacturer, and ii) the scattering (Sij) parameters associated with a transmission line. In order to serve as test vehicles, a chain of inverters...
In this paper we examine the convergence properties of numerical techniques based on harmonic balance for the simulation of ring oscillators. We propose a modification of the continuation method that provides efficient and robust analysis of ring oscillators with moderate number of stages.
In this paper we study the effect of transistor supply voltage and body bias on the performance of ring oscillator Physically Uncloneable Functions (PUFs). The uniqueness (ability to identify a PUF) and reproducibility (ability to reproduce the same output) of PUFs increase drastically in the subthreshold region of operation. Also, the reproducibility of PUFs increase when the transistors are forward...
Phase noise is one of the most restricted specifications in oscillators, especially ring oscillators. Phase noise will exhibit large fluctuations around its nominal value due to the increased process variation with technology scaling. These fluctuations will cause some fabricated ring oscillators not to meet the phase noise constraint and, hence, result in yield loss. This yield loss is expected to...
Negative bias temperature instability (NBTI) has become an important cause of degradation in scaled PMOS devices, affecting power, performance, yield and reliability of circuits. This paper proposes a scheme to detect PMOS threshold voltage (VTH) degradation using on-chip slew-rate monitor circuitry. The degradation in the PMOS threshold voltage is determined with high resolution by sensing the change...
Subthreshold voltage operation, which can be considered an extreme case of voltage scaling, can greatly reduce the power consumption of circuits. This is beneficial in embedded applications that must run off of batteries and scavenged energy. Subthreshold operation has been proven to be very effective by several successful prototypes in the recent years, yet there is no fast and effective way for...
This work proposes a topology using a ring oscillator with sub-feedback loops to generate multiple phases. It is composed of an N-stage main ring (arbitrary N larger than 3) and k-stage sub-feedback loops, where k is not the common divisor of N, N output phases can be obtained. With a linear model analysis, it comes to a result that oscillating frequency is related to k, and the phase difference between...
We illustrate a couple of circuit implementations of molecular devices, chosen as representative examples in the growing field of molecular electronics. On the one side, we discuss the performance of organic thin film transistors and their potential use in inverters and ring oscillators. On the other, we analyze simple electronics components based on single molecules and a cross bar architecture that...
We report a circuit technique to measure the on-chip delay of an individual logic gate (both inverting and non-inverting) in its unmodified form using digitally reconfigurable ring oscillator (RO). Solving a system of linear equations with different configuration setting of the RO gives delay of an individual gate. Experimental results from a test chip in 65 nm process node show the feasibility of...
Quadrature oscillators are effective for clock recovery circuits, complex signal processing, etc. In this report, two new quadrature oscillator circuits based on tetrahedral oscillators are proposed. The proposed quadrature oscillators are simulated and tested by the breadboard circuit in order to verify their electrical performances.
This paper presents a voltage controlled ring oscillator (VCO) with a maximum frequency of 35 GHz and a wide frequency range of 7 GHz. The VCO is designed in a 65 nm technology. This oscillator uses a rectifier doubling technique to achieve higher frequencies. The supply voltage is 1.1 V. The total power dissipation is 15.83 mW. An output power of -6.5 dBm is delivered to a 50 Omega load resistor.
Polymorphic gates can be considered as a new reconfigurable technology capable of integrating logic functions with sensing in a single compact structure. Polymorphic gates whose logic function can be controlled by the level of the power supply voltage (Vdd) represent a special class of polymorphic gates. A new polymorphic NAND/NOR gate controlled by Vdd is presented. This gate was fabricated and utilized...
This paper presents an analytical modeling of ballistic and quasi-ballistic transport, implemented in Verilog-A environment and used for circuit simulation. Our model is based on the Lundstrompsilas approach and uses an expression of the backscattering coefficient given by the flux method. The model takes also into account short channel effects and tales into account the effects of different scattering...
This paper presents modeling of manufacturing variability and body bias effect for subthreshold circuits based on measurement of a device array circuit in a 90 nm technology. The device array consists of P/NMOS transistors and ring oscillators. This work verifies the correlation between the variation model extracted from IV measurement results and oscillation frequencies, which means the transistor-level...
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