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In this PhD dissertation, we propose a new testing approach for effectively managing hardware development risks, producing hardware designs with enough quality and reliability. Our proposal is based on the combination of high-level modelling and a unit testing framework in order to generate real hardware implementations for validating the designer intent, in order to keep a high cycle-accuracy and...
This paper describes a new methodology of construction of the internal activity block of an ICEM-CE model of an FPGA based on a predictive approach using the estimation tools of the dynamic power and the static timing proposed by the manufacturer of the integrated circuit.
A high-throughput architecture of the CCSDS 122.0-B-1 image compression standard is proposed. The architecture uses a novel memory organization in order to reduce the total memory operations and the number of the individual memories allowing operation without external memories. The architecture has been implemented on space grade and commercial FPGA Device. It achieves 136 MSamples/sec on space grade...
This paper presents a framework to evaluate the error rate of a design implemented in an FPGA, depending on the operating conditions. The effects of the operating temperature as well as voltage variation are taken into account. For example, in applications such as the electric vehicle motor control, the non-negligible electromagnetic field can result in FPGA supply voltage variation. It is shown that...
In-house technology for digital beam position measurement is being developed for Indus-2 Synchrotron radiation source. FPGA based digital processing electronics is being designed to acquire the signal from 4-electrode BPM device using 4-channel ADC. These ADC will be calibrated by the spectrum analysis of the input signal. In this paper, High Speed Printed Circuit Board [PCB] will be designed using...
This paper describes a new methodology of construction of the internal activity block of an ICEM-CE model of an FPGA based on a predictive approach using the estimation tools of the dynamic power and the static timing proposed by the manufacturer of the integrated circuit.
This paper describes an on-going work aiming at using FPGAs as a fast prototyping environment for Token-based Self-timed processors, inspired by the Octasic asynchronous design technique. Originally developed for Digital Signal Processing, this design technique is adapted here for an FPGA-based general purpose processor. The paper emphasizes improvements to existing FPGA implementation methodologies...
This paper presents an satellite camera imaging system using area CCD based on FPGA. FPGA was adopted to act as a center unit to generate timing logic signals of the CCD and control the A/D converter, etc. The three-wire serial interface is used to communicate with the management and control system on the satellite. The image data of the CCD is coded by the imaging system and converted to the required...
We present a portable 64-channel photon-counting system employing a monolithic array of Single-Photon Avalanche Diodes (SPADs) and a custom-designed Time-to-Digital Converter (TDC), for single-photon counting and timing applications. The system provides state-of-art singlephoton detection performance and time-resolved measurement capability, with timing precision down to 100 ps FWHM and linearity...
This paper presents a novel calibration technique for charge redistribution digital-to-analog converters (DACs). By using the proposed clock-pulse-width calibration, the clock of the DAC is modulated, and the output voltage is effectively modified to enhance the differential-non-linearity (DNL) and integral-non-linearity (INL). By using this method, the measured DNL, and INL have been improved by...
Timing analysis in embedded systems has focused mainly on the Worst-Case Execution Time (WCET) in the past. This was (and still is) important to make guarantees for the application of the system in safety critical environments. Today, two reasons call for a slightly changed perspective. Firstly, the complex and often unpredictable internal structure of modern system-on-chip architectures prohibits...
This paper describes a cloud-based digital design environment for ASIC and FPGA. We call it CloudV. CloudV is built using open-source as well as homegrown EDA software tools. The ultimate goal of CloudV is to reduce the design costs by relying on cloud infrastructure and on collaborative design. Currently, CloudV v 1.0 allows students to gain hands-on experience in digital ASIC design tasks covering...
A LiDAR ranging system has been developed based on automatic gain control and timing discriminators in this paper. Timing discriminators in the time-pickoff circuit, which employ constant fraction discriminator, were designed to reduce the walk error caused by the variation of pulse amplitude. Automatic gain control was used to concentrate the input pulse amplitude of timing discriminator in a limited...
In this paper we describe a flexible infrastructure that can directly interface unmodified application executables with FPGA hardware acceleration IP in order to 1), facilitate faster computer architecture simulation, and 2), to prototype microarchitecture or accelerator IP. Dynamic binary modification tool plugins are directly interfaced to the application under evaluation via flexible software interfaces...
In view of the problem that the unfixed CRC calculation and the compatibility with gigabit Ethernet are the two questions during design of ten gigabit Ethernet MAC controller. This paper solves the above two questions according to the proposed solution. CRC calculation module can be designed to be a fast calculation speed and low gate delay by using a new type CRC method which contains the preprocessing...
Process variability is known to be increasing with technology scaling in IC fabrication, thereby degrading the overall performance of the manufactured devices. The current paper focuses on the variability effect in FPGAs and the possibility to boost the performance of each device at run-time, after fabrication, based on the individual characteristics of this device. First, we develop a sensing infrastructure...
Upcoming mobile communication systems are more complex and comprise of sophisticated functionality to enhance their performance. To expedite their time to market, the RTL development and verification cycle time has to be improved. This paper puts an emphasis to improve the prototyping phase by using Model Based Design technique comprising of Simulink HDL coder, HDL verifier and rapid FPGA prototyping...
Among the various memories, Ternary Content Addressable memory (TCAM) is used to give a high speed of searching operation. In ordinary memories, like static random access memories (SRAM), the address is given and data is given as output, but in TCAM the data is given as input and address is given as output. However it is having some disadvantages like less bit density, slow access time, more searching...
In access-network-chip testing and verification, problems occur mostly on I2C control interface because of its complicated protocol and high requirement on reliability, using an automated testing tool with simple operation and high testing coverage could ensure the quality of chip as well as shorten the chip development cycle. The paper designs an automated system based on 5SGXEA7N2F45C2 FPGA chip...
As the development of a viable quantum computer nears, existing widely used public-key cryptosystems, such as RSA, will no longer be secure. Thus, significant effort is being invested into post-quantum cryptography (PQC). Lattice-based cryptography (LBC) is one such promising area of PQC, which offers versatile, efficient, and high performance security services. However, the vulnerabilities of these...
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