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This paper presents a new transceiver for impulse radio ultra-wideband (IR-UWB) systems. This work is related to CHIST-ERA SMARTER project (Smart Multifunctional Architecture and Technology for Energy aware wireless sensoRs) which address autonomous wireless sensors nodes. The ultra low-power transceiver consists of an on-off keying (OOK) modulator/demodulator and a pulse generator. To reduce power...
We present an energy efficient QRS detector for real-time ECG signal processing implemented in ASIC. An adaptive thresholding scheme based on forward search interval (FSI) algorithm together with simple preprocessing is proposed to accurately detect QRS peaks. The Verilog HDL codes with improved hardware utilization efficiency are validated using FPGA, achieving 99.59% sensitivity (Se) and 99.63%...
The security of Internet of Things (IoT) devices including consumer products has been pointed out. Therefore, authenticated encryptions, which perform both encryption and authentication, have been attracted attention. SIMON-JAMBU is a lightweight authenticated encryption and it passed the second round of CAESAR which determines the standard of authenticated encryptions. Regarding security of hardware,...
The semiconductor counterfeiting has become a serious problem. Physical Unclonable Function (PUF) is attracted attention as a countermeasure. PUF can generate a unique ID for each device utilizing a variation during manufacturing. However, PUF is vulnerable to modeling attacks. In addition, it is reported that side-channel information allows modeling attacks effectively. To secure the safety of semiconductors,...
As fault-tolerant Networks-on-Chip (NoCs) become prevalent in reliable systems, their overhead must be accurately evaluated. In this paper, we evaluate the overhead of a soft error resilient real-time NoC router for ASICs in terms of area and power. We employ a power analysis framework and load profiles that provide accurate power figures. Furthermore, we analyze the power behavior in normal operation...
A new power estimation approach based on the decomposition of a digital system into basic operators is presented. This approach aims to estimate the energy consumption at early design phases of digital blocks implemented on FPGAs. Each operator has its own model which estimates the switching activity and the power consumption. By interconnecting several operators, statistical information is then propagated...
Today, artificial neural networks (ANNs) are widely used in a variety of applications, including speech recognition, face detection, disease diagnosis, etc. And as the emerging field of ANNs, Long Short-Term Memory (LSTM) is a recurrent neural network (RNN) which contains complex computational logic. To achieve high accuracy, researchers always build large-scale LSTM networks which are time-consuming...
Content addressable memory (CAM) performs parallel data search at the cost of high area and power penalty. We propose a high-speed 6T-ReCSAM (Reconfigurable CAM/SRAM) with new energy efficient sensing technique. Proposed implementation is compatible with compact 6T-SRAM foundry bitcells. Test-macro of 8Kb is implemented in 28nm FDSOI CMOS and reaches up to 1.56GHz at 0.9V with 0.13fJ/bit energy consumption...
Due to the features of FPGA architectures such as high performance and reconfiguration at run time, they have become remarkable contenders for many mission critical applications, much beyond rapid prototyping only. As the feature size of the semiconductor technology shrinks, also FPGA-based systems using underlying nano-technologies suffer from age-induced parameter deterioration that may finally...
Nowadays, SoC uses Network on Chip (NoC) to connect its increasing number of building blocks. FPGAs, like SoCs, can use NoC to connect its increasing number of tiles, memories, DSP slices and embedded processors. But one drawback of using NoC is that increasing its router ports will affect the area, power and frequency of the system significantly. For FPGAs to benefit from the NoC approach we have...
This paper proposes a method for FPGA-based space-borne systems supporting multi-task applications to enable run-time combined adaptation to variations in system power budget and variations in available hardware resources due to occurrence of transient or permanent faults. The adaptation method assumes that each task in the workload has multiple implementations, which can operate at different clock...
Platforms with different computation resource, e.g. CPUs and FPGAs, become one of the first choices to deploy performance-requiring embedded applications. On this technology, functionalities can be implemented either as hardware (HW) or software (SW) components. Here, we extend the MultiPar methodology to support the selection of optimal partitioning solutions with respect to system properties. We...
In this paper, we design Tetris game which can rotate, generate randomly blocks, eliminate rows, and get scores based on FPGA. Multi-bit Flip-flops (MBFF) concept is implemented into a part of Tetris game to save power consumption and clock buffer area. The 2-bit MBFF and 4-bit MBFF technique are compared with the Single-Bit Flip-flop. Results show that Multi-bit Flip-flops technique is very effective...
Algorithms of dense stereovision can be of great interest for designing computer vision systems of autonomous mobile objects. In the process of computing dense stereo, on the one hand, a lot of arithmetic operations are performed and a significant memory resource is required, and, on the other hand, the majority of dense stereovision algorithms can be parallelized. Different modern computer architectures...
This paper describes a new methodology of construction of the internal activity block of an ICEM-CE model of an FPGA based on a predictive approach using the estimation tools of the dynamic power and the static timing proposed by the manufacturer of the integrated circuit.
CMOS power dissipation has multiple components: switching, short-circuit, and static. In order to be robust to power attacks, digital logic should eliminate the relation between processed data and each and every power component. Other sources of side-channel information are glitches and the early evaluation of signals. We improve over our previous work and propose a Look-Up Table (LUT) with increased...
The Internet of Things (IoT) and cloud computing rely on strong confidence in security of confidential or highly privacy sensitive data. Therefore, side-channel leakage is an important threat, but countermeasures require expert-level security knowledge for efficient application, limiting adoption. This work addresses this need by presenting the first High-Level Synthesis (HLS) flow with primary focus...
Heterogeneous compute nodes in form of CPUs with attached GPU and FPGA accelerators have strongly gained interested in the last years. Applications differ in their execution characteristics and can therefore benefit from such heterogeneous resources in terms of performance or energy consumption. While performance optimization has been the only goal for a long time, nowadays research is more and more...
In this paper, we propose a three-stage reconfigurable topology synthesis approach for Application-Specific NoC (ASNoC) on partially dynamically reconfigurable FPGAs, where the topology is reconfigured dynamically at run-time along with the application’s execution. Firstly, given the scheduling and floorplanning of task modules, an Integral Linear Programming (ILP)-based method is proposed to partition...
Since Internet of Things (IoT) is widely used, IoT security is very important. Therefore, authenticated encryptions, which realize data encryption and the authentication between devices simultaneously, have been attracted attention. MORUS is one of the most popular authenticated encryptions. Regarding hardware security, the threat of power analysis attack is pointed out. However, power analysis attack...
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