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Laboratories and project work are widely used in the engineering curricula around the world. Such hands-on trainings allow the students to learn hard-as well as soft-skills and can be used to prepare them for the work in the industry. In microelectronics education laboratories are often offered. For such a laboratory the authors present a set-up to teach microelectronic design using a top-down design...
The FPGA compilation process (synthesis, map, place, and route) is a time consuming task that severely limits designer productivity. Compilation time can be reduced by saving implementation data in the form of hard macros. Hard macros consist of previously synthesized, placed and routed circuits that enable rapid design assembly because of the native FPGA circuitry (primitives and nets)which they...
The Lightfield descriptor method for 3D computer graphics offers the highest quality object retrieval from a database at the expense of higher storage and computational cost vs. other methods. This paper presents two special purpose architectures, based on FPGAs and GPUs, for the depth buffer extraction algorithm which is used by the Light field Descriptor method. The two architectures were fully...
Parallel-prefix adders (also known as carry-tree adders) are known to have the best performance in VLSI designs. However, this performance advantage does not translate directly into FPGA implementations due to constraints on logic block configurations and routing overhead. This paper investigates three types of carry-tree adders (the Kogge-Stone, sparse Kogge-Stone, and spanning tree adder) and compares...
Communications in the aerospace environment is often very challenging. These challenges increase with the demand for higher data rates. This paper focuses on design and implementation of synchronization circuits for Direct Sequence Spread Spectrum (DSSS) receivers using Field Programmable Gate Arrays (FPGAs). In aerospace communications, it is the wireless digital communications receiver which bears...
FPGAs are a great platform for studying within-die process variation because test structures can be implemented in product silicon using reconfigurable logic. This approach can achieve very high coverage without wasting otherwise useful silicon area. In this paper, we present a detailed analysis of within-die delay variation in a 65nm FPGA. We use densely distributed test oscillators to measure within-die...
For most of the applications that make use of a vector coprocessor, the resources are not highly utilized due to the lack of sustained data parallelism, which sometimes occurs due to vector-length changes in dynamic environments. The motivation of our work stems from (a) the mandate for multicore designs to make efficient use of the on-chip resources, (b) the frequent presence of vector operations...
Reconfigurable Field Programmable Gate Arrays (rFPGAs) are employed extensively in spacecraft electronic systems to implement low-power adaptable systems that provide high density functionality. A challenge that must be tackled during system design is their high susceptibility to radiation induced Single Event Upsets (SEUs). A burst of energized particles may cause extensive damage to circuits. Even...
In this paper we propose a design methodology to explore dynamic and partial reconfiguration (DPR) of modern FPGAs. We define a set of rules in order to model DPR by means of UML and design patterns. Our approach targets MPSoPC (Multiprocessor System on Programmable Chip) which allows: a) area optimization through partial reconfiguration without performance penalty and b) increased system flexibility...
This paper presents a 4-channel ICA implementation in the separation of EEG signals for on-line monitoring and analysis of brain functionalities. A novel ICA architecture utilizing mixed sequential, pipelined, and parallel processing units and employing interleaved and circular-based RAM modules to achieve hardware-efficient design is presented. The ICA processor is fabricated using UMC 90nm High-Vt...
Modern hardware and software implementations of cryptographic algorithms are subject to multiple sophisticated attacks, such as differential power analysis (DPA) and fault-based attacks. In addition, modern integrated circuit (IC) design and manufacturing follows a horizontal business model where different third-party vendors provide hardware, software and manufacturing services, thus making it difficult...
The design flow of Fast Fourier Transform devices development using the method of algorithmic operation devices synthesis from graphical representation of algorithms is proposed. Their automatic synthesis for various numbers of input data with different word length and their comparative evaluation are performed.
In this paper, we proposes a novel hardware architecture of face-detection engine for mobile applications. We used MCT (Modified Census Transform) and Adaboost learning technique as basic algorithms of face-detection engine. We have designed, implemented and verified the hardware architecture of face-detection engine for high-performance face detection and real-time processing. The face-detection...
In today's world there is a growing demand for real-time implementation of cryptographic algorithms which are being used in secure communication systems, networks and security systems. Traditional computing techniques involved the use of application specific integrated circuits to achieve high performance but with extremely inflexible hardware design meanwhile the flexibility of hardware design was...
Power Integrity (PI) is a popular topic in today's electronic equipment industry because recent electric equipment uses various ICs, ex. Microprocessor, Memory, FPGA and ASIC. In addition, PI typically has lower source voltage and larger current required. To realize robust design, better power distribution network (PDN) is required. Good PDN means it can supply stable source voltage even if source...
An increasing number of applications rely on embedded systems for a correct behavior or user interaction. Many of these systems are today considered critical (for safety, security ... or just for competitiveness), but cannot be expensive and often need flexibility. SRAM-based FPGAs are good candidates to implement such systems but their main disadvantage is their relatively high probability of application...
The main objective of this educational paper is to provide an updated survey of ASIC and FPGA technologies' convergence in reconfigurable and embedded systems. Through the analysis of design methodologies and strategies facing multi-core and power consumption challenges we will follow that evolution approaching ASIC and FPGA architectures on the embedded systems arena.
Although software engineers have high performance algorithms that could be implemented power-efficiently as embedded Systems on Chip (SoC) with modern FPGAs, there is still no easy path for them to a hardware realization, mainly due to the lack of appropriate design tools. We present an overview of a tool we have developed to boost the productivity of processor-centric SoC designs for FPGAs. Our tool...
Multi-Processor Systems on Chip (MPSoCs) have been proposed as a promising solution for the increasing demand of computational power required for recent application. The parallelization through SIMD (single instruction/multiple data) architectures has been a proven solution to speed up the processing of the recent application that exhibit massive amounts of data parallelism. The level of parallelism...
As fabrication process technology continues to advance, mask set costs have become prohibitively expensive. Structured ASICs can offer price and performance between ASICs and FPGAs. They are attractive for mid-volume production and offer good intellectual property security. In this paper, a structured ASIC methodology, where 2 metal- and 1 via-mask are customised, is described. The CAD tools are fully...
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