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Recently, a new lightweight block cipher, SKINNY, has been proposed by Beierle et al. in Annual Cryptology Conference 2016. This paper presents an area-efficient FPGA implementation of SKINNY block cipher. In this paper, a new column-serial structure is proposed to speed up SKINNY without compromising its area cost, and the implementation of SKINNY S-box is optimized by utilizing FPGA embedded dual-port...
Polar codes are the first class of forward error correction (FEC) codes with a provably capacity-achieving capability. Using list successive cancellation decoding (LSCD) with a large list size, the error correction performance of polar codes exceeds other well-known FEC codes. However, the hardware complexity of LSCD rapidly increases with the list size, which incurs high usage of the resources on...
Quadrature downconversion impairments should be taken into account and compensated to the increasing of the Direct Conversion Receiver (DCR) reception quality. DC-offset and I/Q-imbalance are fitted into this group. Experimental estimation of two relatively simple compensation methods for the indicated drawbacks is reviewed in the paper. Energy efficiency and computational complexity estimation are...
In this paper, FGPA implementations of amplitude and phase comparison direction finding methods are presented. In amplitude comparison direction finding (AC-DF), the power ratio between the receiver channels is compared with the values in the look-up-table that is generated using antenna patterns. In phase comprison direction finding (FC-DF), basically the phase difference is extracted between channels...
This paper simplifies the chase decoding algorithm for TPC codes for a particular modulation scheme (BPSK). Without reducing the decoding performance, the multiplication of the new algorithm is 33% of the original algorithm. The access algorithm of receiving matrix [R] is also optimized, and the access time of receiving matrix [R] is reduced to 3%. Finally, the 800M bps TPC decoder was implemented...
We present a field programmable gate array (FPGA) based implementation of the H.264 video decoder algorithm. The novelty of our design is that the communication between the decoder modules is done using a network-on-chip (NoC). This makes our design scalable and easily integrated within larger future NoC based systems, where the same hardware platform can host other algorithms such as compression,...
The article presents an evaluation of sound source localization algorithm based on field-programmable gate array (FPGA) and ARM processor. The proposed architecture performs the computation of azimuth and elevation angles of the speaker location in a real-time. Time-difference of arrival (TDOA) features are computed for a grid with four microphones. The speaker position is estimated by matching the...
For the rapid response and security requirements of network communication, this paper develops a new implement method of encryption and authentication scheme SM4-GCM on FPGA with low resource occupancy and fast processing speed. This method adopts the SM4 algorithm with independent intellectual property rights. Two SM4 modules are used during encryption to improve the data processing speed by Ping-Pong...
Digital images can be represented in different forms/representations by using Image Transforms, which are simple or complex mathematical operations on the image. These transforms finds application in compression, enhancement, pattern recognition, and feature extraction etc. Discrete Wavelet Transform (DWT) is a widely used wavelet transformation. DWT transforms image from space domain to frequency...
Because of their excellent error correction performance, Low-Density Parity Check Codes (LDPC) have become the most widely used technique for forward error correction in almost all modern communications applications. This paper introduces an FPGA implementation of a partial parallel, flexible LDPC decoder based on the Min-Sum decoding algorithm. The suggested architecture uses a combination of unicast...
This paper discusses the design and successful implementation of a packet based Multichannel satellite modulator using efficient, novel Data buffering technique. The modulator receives data from IP network and transmits it to satellite network. The scheme allows for loss-less transfer of data from Best effort IP based packet network to a circuit switched fixed bit rate narrow band continuous satellite...
The security of cryptocircuits is today threatened not only by attacks on algorithms but also, and above all, by attacks on the circuit implementations themselves. These are known as side channel attacks. One variety is the Active Fault Analysis attack, that can make a circuit vulnerable by changing its behavior in a certain way. This article presents an experimental fault insertion attack on an FPGA...
The article presents the evaluation of configurable hard-core for disparity map computation based on FPGA. The proposed hardware architecture performs the computation of disparity map in a pipelined order. The local block matching based on sum of absolute differences is performed for the search of corresponding similarities in two stereo images. The disparity core is implemented on Virtex-4, Artix-7,...
This article presents the development of an experimental system to introduce faults in Trivium stream ciphers implemented on FPGA. The developed system has made possible to analyze the vulnerability of these implementations against fault attacks. The developed system consists of a mechanism that injects small pulses in the clock signal, and elements that analyze if a fault has been introduced, the...
In this work, an architecture of low complexity non-linear Decision Feedback Equalizers is proposed, where the parallel filters of the feed-forward section are hardware-efficient structures based on Iterated Short Convolution. For the design of the parallel filters an algorithm is proposed, which provides an architecture with regularity that is more suitable for FPGA implementation. The proposed architecture...
The FPGA implementation of lattice-ladder multilayer perceptron with its training algorithm seems attractive, however there is a lack of experimental results on its efficiency. The main aim of this investigation was to optimize the latency and DSP block usage for the normalized lattice-ladder neuron (LLN) and its simple gradient training algorithm implementation on FPGA. Four alternative regressor...
In this paper, we describe the design of a configurable Memory Management Unit (MMU) and its prototype implementation on a Field Programmable Gate Array (FPGA). We present analytical results of scaling the size of the second level software-managed Unified Translation Lookaside Buffer (UTLB) in terms of effect on the overall hit rate. Three design-time configurations with 16, 32, and 64 entries were...
This paper presents a compact and efficient hard output MIMO detection and its FPGA implementation. Our method is based on a complex-valued decomposition and a highly compact expansion, which needs least number of visited nodes and a half of tree depth than previously published K-best designs. We propose a fully pipelined architecture, combining with resource sharing to realize the detector. Furthermore,...
High Efficiency Video Coding (HEVC), the recently developed international video compression standard, has 50% better video compression efficiency than H.264 video compression standard at the expense of significantly increased computational complexity. HEVC Inverse Discrete Cosine Transform (IDCT) algorithm accounts for 11% of the computational complexity of an HEVC video encoder. Recently, commercial...
The concept of a More Electric Aircraft (MEA) power system is becoming increasingly popular, mainly due to its higher efficiency as compared to the conventional aircraft power system. This paper proposes and implements a section of an MEA system in real-time. The real-time implementation methodology presented in this paper utilizes both CPU-cores and an FPGA processor, depending on the time step requirement...
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