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Increasing environmental pollutions, lack of power in remote places and demand for more energy makes us to seek new energy sources. Wind and solar hybrid energy have being popular ones owing to abundant, complement nature, ease of availability and convertibility to the electric energy. For hybridizing solar-wind system DC-AC or separate DC-DC converters are used one for each source. They will be connected...
Phase-locked loops (PLLs) are doubtless the most popular synchronization technique in the power converters. Almost all proposed PLL structures known in literature are inherently nonlinear and can be linearized as second order linear time invariant system. Nonlinear nature of PLLs degrades their performances, and question arises if there exist an enhanced PLL structure that would have superior performances...
A new power estimation approach based on the decomposition of a digital system into basic operators is presented. This approach aims to estimate the energy consumption at early design phases of digital blocks implemented on FPGAs. Each operator has its own model which estimates the switching activity and the power consumption. By interconnecting several operators, statistical information is then propagated...
The widely accepted block-matching technique, which is required to identify motion vectors, fails in cases in which texture is not existent. In [1], we proposed a hardware-oriented cellular-automaton algorithm that generates spatial patterns on textureless objects and backgrounds, aiming at motion-vector estimation of textureless moving objects. This demonstration presents a field-programmable gate...
Fine-grained runtime power management techniques could be promising solutions for power reduction. Therefore, it is essential to establish accurate power monitoring schemes to obtain dynamic power variation in a short period (i.e., tens or hundreds of clock cycles). In this paper, we leverage a decision-tree-based power modeling approach to establish finegrained hardware power monitoring on FPGA platforms...
This paper describes a new methodology of construction of the internal activity block of an ICEM-CE model of an FPGA based on a predictive approach using the estimation tools of the dynamic power and the static timing proposed by the manufacturer of the integrated circuit.
The Frisch-Waugh-Lovell (FWL) Recursive Least Squares (RLS) algorithm has been recently proposed as an RLS algorithm with lower computational cost and better numerical properties. We propose a VHDL implementation that has been successfully implemented on a Xilinx Virtex-7 FPGA. The FWL RLS algorithm has a complexity of L2 + O(L) products, instead of 1.5L2 O(L) as in conventional RLS algorithms. Because...
As the importance of the thermal issues in the design of multiprocessor systems increases, it becomes mandatory to analyze the thermal effects and the thermal management techniques early in the design flow, ideally during the hardware emulation phase. Moreover, several scenarios (multiprocessor systems connected with photonic NoCs, 3D systems, etc.) demand a high accuracy during the thermal emulation...
The trend of using heterogeneous computing and HW/SW-Codesign approaches allows increasing performance significantly while reducing power consumption. One of the main challenges when combining multiple processing devices is the communication, as an inefficient communication configu-ration can pose a bottleneck to the overall system performance. To address this problem, we present a methodology that...
Latest researches related to Wide Area Measurement Systems (WAMS) recommends the development of a cost-effective FPGA based phasor measurement unit for developing a real time synchrophasor network. This paper presents an algorithm for an FPGA based Phasor Measurement Unit (PMU) modeled using Xilinx Vivado System Generator design suite. The backbone of the proposed PMU algorithm is the Non Recursive...
This paper examines the single-event upset response of a customer memory interface design on the Xilinx 20nm XCKU040 Field Programmable Gate Array (FPGA) irradiated with 64MeV proton source. Results for single-event upsets on configuration RAM (CRAM) cells are provided. The difference between architectural vulnerability factor (AVF) and design vulnerability factor (DVF) of the customer memory interface...
Quadrature downconversion impairments should be taken into account and compensated to the increasing of the Direct Conversion Receiver (DCR) reception quality. DC-offset and I/Q-imbalance are fitted into this group. Experimental estimation of two relatively simple compensation methods for the indicated drawbacks is reviewed in the paper. Energy efficiency and computational complexity estimation are...
This paper describes a new methodology of construction of the internal activity block of an ICEM-CE model of an FPGA based on a predictive approach using the estimation tools of the dynamic power and the static timing proposed by the manufacturer of the integrated circuit.
This paper proposed real-time lane detection system for automotive application based on field programmable gate array (FPGA). The proposed system has two main. The first one is pre-processing with statistic and blob detection, and the second one is real-time lane detection algorithm. To meet real-time system, using the simple algorithm on a clear image by pre-processing. Experiments and comparisons...
This article shown an FPGA implementation on estimation of fundamental frequency of three-phase power system based on widely linear ACLMS algorithm. The frequency estimator using FPGA is proposed with a view applications in active microgrids. The main goal oh this article is to depict some practical issues that must be taken care during the algorithm implementations for reach this aim, as like: numerical...
The application of Phasor Measurement Units (PMUs) to the real-time monitoring, protection and control of Distribution Networks, requires the availability of high accuracy devices that are characterized at the same time by a reasonable cost. This paper presents the design of a low-cost PMU prototype based on a Field Programmable Gate Array (FPGA) that integrates a recently published synchrophasor...
This paper describes the architecture of a wearable, wireless embedded system for the Diabetic Peripheral Neuropathy (DPN) assessment in ordinary dynamic movements, such as a fluid gait. In this context, the EMG analysis can provide information about the nerves status by estimating the linked Muscle Fiber Conduction Velocity (MFCV). The system operates with synchronized and digitized data samples...
Packing and placement are two crucial stages for FPGA realization. In the design flow, the basic logic units, such as look-up-tables (LUTs) and flip-flops (FFs), have to be merged into configurable logic blocks (CLBs) before placement. How the basic logic blocks are clustered in the packing stage has a great impact on the placement quality. This work presents an analytical placement framework for...
This paper discusses the design and implementation of a Digital Pre-Distortion (DPD) system for RF power amplifier (PA) linearisation in an in-house designed Software Defined Radio (SDR) platform. An indirect learning approach using orthogonal memory polynomial model is adopted for the DPD design. Important aspects of the SDR architecture relevant to DPD implementation are outlined. Several techniques...
This paper describes the design, experimental assessmant and Software Defined Radio (SDR) implementation of a Secondary User (SU) link for the IEEE DySPAN Challenge 2017. The objective is to successfully discern the behavior of and coexist with a Primary User (PU), whose channel access patterns vary over time. For that end, we utilize sensing, deep learning and dynamic optimization.
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