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This paper presents a real-time Kvazaar HEVC intra encoder for 4K Ultra HD video streaming. The encoder is implemented on Nokia AirFrame Cloud Server featuring a 2.4 GHz dual 14-core Intel Xeon processor and Arria 10 PCI Express FPGA accelerator card. In our HW/SW partitioning scheme, the data-intensive Kvazaar coding tools including intra prediction, DCT, inverse DCT, quantization, and inverse quantization...
Efficient and robust wireless video delivery is an enabling technology for various applications. The existing wireless video transmission scheme has the cliff effect and it cann't gracefully adapt to channel variations. In this paper, we introduce a pseudo-analog wireless video transmission improvements and design in the hardware. Comparing with the traditional transmission, the linear processing...
The Kiwi project revolves around a compiler that converts C# .NET bytecode into Verilog RTL and/or SystemC. An alpha version of the Kiwi toolchain is now open source and a user community is growing. We will demonstrate an incremental approach to large system assembly of HLS and blackbox components, based on an extended IP-XACT intermediate representation. We show how to address multi-FPGA designs...
Networks-on-chip (NoCs) have become a new chip design paradigm as the size of transistors continues to shrink. Globally-asynchronous locally-synchronous (GALS) on-chip networks are proposed for solving issues such as large clock tree distribution and signal delay variations. More interestingly, for the GALS networks using m-of-n delay-insensitive interconnect, the asynchronous interconnect not only...
Encoders using generator polynomials and linear-feedback shift registers are the key parts of communication technologies widely used in most of today's integrated as well as field systems. This paper presents a detailed comparison of three ways of implementation of configurable encoders arranged in PENCA and implemented in Xilinx and Altera FPGAs.
Failure tolerant data encoding and storage is of paramount importance for data centers, supercomputers, data transfers, and many aspects of information technology. Reed-Solomon failure erasure codes and their variants are the basis for many applications in this field. Efficient implementation of these codes is challenging because they require computations in Galois fields, which are not supported...
In this paper, a novel scalable and resource-efficient architecture capable of monitoring the compressibility of a data stream with various entropy encoding algorithms is proposed. The self-adaptive architecture determines the best compression technique among many techniques which may be selected to encode an online data stream. This information can be used to reconfigure an adaptive encoding architecture...
Controllers based on Synchronous Finite State Machines (SFSM) are widely used in the design of digital hardware and that can be implemented in Field Programmable Gate Arrays (FPGAs). A class little known and very interesting of SFSM in the FPGA platform is the SFSMs of direct output (SFSM_DO). These state machines use the output signals as state signals, thus allowing several advantages when compared...
Cognitive and software defined radios require ultrawideband (UWB) antennas with digital beamforming. Recently, a novel on-site coding receiver (OSCR) architecture was proposed to significantly reduce hardware requirement for digital beamforming. At the receiver side, we propose to code several antenna outputs in the analog domain prior to digitizing them using a single analog-to-digital converter...
Digital video compression techniques have an important role that makes transmission and storage of multimedia content in bandwidth and storage space limited environment efficient. This paper describes 3D video coding using FPGA encoder architecture for newer and more reliable multimedia technologies to drive the industry to improve services in the field of entertainment marketing, to encourage the...
In this invited paper, we describe a rate-adaptive FEC scheme based on LDPC codes together with its software reconfigurable unified FPGA architecture. By FPGA emulation, we demonstrate that this class of rate-adaptive LDPC codes based on shortening with an overhead from 25% to 42.9% provides a coding gain ranging from 13.08 dB to 14.28 dB at a post-FEC BER of 10−15 for BPSK transmission. In addition,...
In this invited paper, both binary and nonbinary LDPC codes suitable for optical transmission systems are described. The corresponding FPGA implementation has been discussed as well. The use of adaptive LDPC coding to deal with time-varying optical channel conditions is described as well.
This paper presents the design of a new hardware accelerator, filtering the input data using Gabor functions and dedicated to image processing. The proposed design obtains a great reduction in terms of resources if compared to other state-of-the-art implementations. This is done exploiting the separability of Gabor filters along certain orientations and through a reorganization of the arithmetic units...
In this paper, a positioning system is designed based on the visible light communication (VLC) technology for the tracking of mobile target in the indoor environment. The practical received signal strength (RSS) can be measured for subsequent positioning algorithm by using the designed system. Based on the practical measurements, an empirical equation is proposed to estimate the target's distances...
Spike generation and routing is typically the most energy-demanding operation in neuromorphic hardware built using spiking neurons. Spiking neural networks running on neuromorphic hardware, however, often use rate-coding where the neurons spike rate is treated as the information-carrying quantity. Rate-coding is a highly inefficient coding scheme with minimal information content in each spike, which...
This paper presents a lossless, low latency, low power dissipation compression for long-term wearable ECG monitor to reduce the amount of data, avoiding costly unnecessary wireless data transmission to extend battery life. In this research, we introduce an approach base on run-length coding, which compresses ECG signal by preforming duplicate data encoding by using the characteristics of ECG signal...
Polar code has become a major milestone in information theory field in recent times. Researchers are still observing more efficient encoding and decoding structures. In this study, a new WIB based structure is proposed which reduces the computational complexity of WIB introduced as an early termination method for BP polar decoder in literature. Both proposed and WIB methods are implemented with VHDL...
The number of IPs running concurrently on an FPGA has increased in recent years. Communication among these IPs has necessitated the introduction of the network on chip (NoC) for low-power, high-performance, and scalable on-chip networking. While NoCs are superior to traditional shared buses, there is an attendant resource overhead incurred by the NoC links, routers and network adapters. We present...
This paper simplifies the chase decoding algorithm for TPC codes for a particular modulation scheme (BPSK). Without reducing the decoding performance, the multiplication of the new algorithm is 33% of the original algorithm. The access algorithm of receiving matrix [R] is also optimized, and the access time of receiving matrix [R] is reduced to 3%. Finally, the 800M bps TPC decoder was implemented...
We propose a novel end-to-end framework to customize execution of deep neural networks on FPGA platforms. Our framework employs a reconfigurable clustering approach that encodes the parameters of deep neural networks in accordance with the application's accuracy requirement and the underlying platform constraints. The throughput of FPGA-based realizations of neural networks is often bounded by the...
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