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Built-in self-repair (BISR) approach utilized mostly in regular structures of memory cores has been a promising approach to increase the reliability of any type of integrated circuit. BISR considers spare blocks which in the case of a fault occurrence are used to replace defected circuit parts. A new fault detection and repair procedure with a generic BISR architecture for logic cores is presented...
The present work proposes an improved PSPICE implementation of the equivalent electrical model of silicon photomultipliers (SiPMs) to simulate and predict their transient response to avalanche trigger events. In particular, the developed model provides a detailed investigation of magnitude and timing of the read-out signals and can therefore be exploited to perform reliable circuit-level simulations...
The EER (Envelope Elimination and Restoration) architecture is high efficient power control method for high frequency power amplifiers. The EER architecture has a feature of high efficiency operation for the high PAPR system such as QAM and OFDM. However, due to slow transient attenuation of the tuned power amplifiers, actual EER system cannot achieve expected power level and efficiency. In order...
The EER transmission system was introduced to exploit high efficiency switching power amplifiers in the high PAPR transmission systems such as QAM and OFDM. However, due to transient attenuation characteristics of the tuned switching power amplifiers, EER systems suffered from low power efficiency in the actual transmission systems. EPWM architecture was introduced to improve power efficiency of the...
This paper describes a neutron-induced single event effect test in analog-to-digital converters of a Microsemi's programmable commercial mixed-signal system-on-chip. The main objective is to investigate the reliability of the charge redistribution successive approximation register architecture of the analog-to-digital converters (SAR-ADC) embedded into this device, considering critical application...
This paper describes an analytical study of synchronous logic gate design based on hybrid structure with MOS and resistive switching non-volatile memories (RS-NVMs). This type of structure allows ultra-low power consumption during power down, while often-used data are saved in RS-NVM cells. The parallel data sensing achieves low-power and fast computation time. The logic gate construction theory,...
Emerging non-volatile memories (NVM) such as STT-MRAM and OxRRAM are under intense investigation by both academia and industries. They are based on resistive switching mechanisms and promise advantageous performances in terms of access speed, power consumption and endurance (i.e. >1012), surpassing mainstream flash memories. This paper presents a non-volatile full-adder design based on complementary...
The main resources used in electricity generation are becoming fewer, while the impact of renewable resources is still quite small. To allow the necessary time for the technology of renewable resources to mature, a requirement is to increase the energy efficiency. In this regard the smart grid concept was implemented, but whose efficiency depends on creation of a framework through which the end user...
Global industries, governments, organizations, and institutions rely on the operation of datacenters in order to successfully meet their day-to-day objectives. The increased reliance on datacenters combined with the growth of the industry sector has led to more careful considerations for datacenter design. Stakeholders in the datacenter industry have begun to consider alternative electrical distribution...
A switching-sequence-based control scheme for power electronics networks is presented in this paper. The proposed scheme guarantees global stability while meeting predefined performance criteria. First, using techniques based on composite Lyapunov functions and piecewise-linear models of the system, the set of switching sequences that guarantee global stability, is determined. Next, by solving optimization...
Due to their reconfigurability and their high density of resources, SRAM-based FPGAs are more and more used in embedded systems. For some applications (Pay-TV,Banking, Telecommunication ...), a high level of security is needed. FPGAs are intrinsically sensitive to ionizing effects, such as light stimulation, and attackers can try to exploit faults injected in the downloaded configuration. Previous...
The paper addresses the problem of creating a comprehensive fault injection environment, which integrates and improves various simulation and supplementary functions. This is illustrated with experimental results.
Polymorphic gates can be considered as a new reconfigurable technology capable of integrating logic functions with sensing in a single compact structure. Polymorphic gates whose logic function can be controlled by the level of the power supply voltage (Vdd) represent a special class of polymorphic gates. A new polymorphic NAND/NOR gate controlled by Vdd is presented. This gate was fabricated and utilized...
In this paper we present a low cost fault-tolerant attitude determination system to a scientific satellite using COTS devices. We related our experience in developing the attitude determination system, where we combine proven fault tolerance techniques to protect the whole system composed only by COTS from the effects produced by transient faults. We detailed the failure cases and the detection, reconfiguration...
In this paper, we present a new technique to improve the reliability of H-tree SRAM memories. This technique deals with the SRAM power-bus monitoring by using built-in current sensor (BICS) circuits that detect abnormal current dissipation in the memory power-bus. This abnormal current is the result of a single-event upset (SEU) in the memory and it is generated during the inversion of the state of...
In this paper, we introduce and evaluate ScaleMesh, a scalable miniaturized dual-radio wireless mesh testbed based on IEEE 802.11b/g technology- ScaleMesh can emulate large-scale mesh networks within a miniaturized experimentation area by adaptively shrinking the transmission range of mesh nodes by means of variable signal attenuators. To this end, we derive a theoretical formula for approximating...
This paper describes a methodology for building a reliable internet core router that considers the vulnerability of its electronic components to single event upset (SEU). It begins with a set of meaningful system level metrics that can be related to product reliability requirements. A specification is then defined that can be effectively used during the system architecture, silicon and software design...
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