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The IoT (Internet of Things) is one of the primary reasons for the massive growth in the number of connected devices to the Internet, thus leading to an increased volume of traffic in the core network. Fog and edge computing are becoming a solution to handle IoT traffic by moving timesensitive processing to the edge of the network, while using the conventional cloud for historical analysis and long-term...
We survey the recent progress in the research and development of RRAM technology in the past decade, ranging from compact models to involving applications. In particular, we first present an overview of the representative compact models that have been developed to capture essential electrical/chemical/thermal properties of RRAM such as IV characteristics, switching dynamics, variability and reliability,...
Virtual switches are a key elements within the new paradigms of Software Defined Networking (SDN) and Network Function Virtualization (NFV). Unlike proprietary networking appliances, virtual switches come with a high level of flexibility in the management of their physical resources such as the number of CPU cores, their allocation to the switching function, and the capacities of the RX queues, which...
Cloud computing is one of the key innovations in this era of technology. Fuelling us into a century of massively distributed cloud applications and services, cloud applications can be accessed with the greatest of ease simply via a web browser. As we advance further into this world of cloud computing, it is highly essential to develop methods to gauge the performance level of the cloud environment...
Data interaction between power consumers and utilities is one of the distinctive features of smart grid. The smart meter plays a core role in data collection and transmission process, which is also considered as one of the most power consuming devices in the whole architecture of distribution power grid. With the large-scale distribution of smart meters in high-density residential communities and...
Many-core architectures are promising hardware to design hard real-time systems as they are based on simpler and thus more predictable processors than multi-core systems. However, the worst-case behavior of the Network-on-Chip (NoC) for both inter-core and core to external memories or peripherals communications must be established. Several NoCs targeting hard real-time systems, made of specific hardware...
As consumer pressure for more bits per dollar and higher density-per-solid-state disk (SSD) forces manufacturers to squeeze more than one bit per flash cell and feature sizes downwards, wear-out is again becoming an increasing concern. Specifically, while single-level cell flash at larger feature sizes used to boast over 100,000 program/erase (P/E) cycles, modern triple-level cell flash can only sustain...
The design and implementation of a multitasking run-time system on a tightly coupled FPGA-CPU platform is presented. Using a mix of CPU and FPGA programmable logic for computing, user applications are executed as mixed-architecture processes from the perspective of the OS. Context switching mechanisms with hybrid scheduling containing both blocking and preemption support were implemented to support...
Software-defined Networking (SDN) has emerged as the dominant programmable network architecture that separates the control plane from the data plane. SDN allows the network administrators and data centers to efficiently and flexibly manage their networking equipment using software that runs on external servers. SDN adopts OpenFLow protocol to communicate between network switch and controller. In this...
The desire to increase the share of renewable energies in the electricity mix induces a significant rise of volatile energies. A solution to manage these non-dispatchable renewable resources is to deploy new energy storage and demand response systems, gathered together within a smart grid. Our overall objective is to propose an approach to manage smart grids like any other power plant in order to...
In recent years, the use of accelerators in conjunction with CPUs, known as heterogeneous computing, has brought about significant performance increases for scientific applications. One of the best examples of this is Lattice Quantum Chromo-Dynamics (QCD), a stencil operation based simulation. These simulations have a large memory footprint necessitating the use of many graphics processing units (GPUs)...
Due to their good flexibility-performance trade-off, Application Specific Instruction-set Processors (ASIPs) have been identified as a valuable component in modern embedded systems, especially the extensible ones, achieving good cost-efficiency trade-offs. Since the generation of the described hardware is usually automated to a high extent, in order to deliver an ASIP-based design in due time, developers...
In this paper, we propose a 3-stage framed packet switch using an internal speedup of 2 to avoid any control loop between any two stages of the switch. The switch segments the arriving variable-length packets at each input port into fixed-size cells and assembles the cells into frames. Then the frames are switched across the shared buffers to their destined output ports, and the cells are reassembled...
Our daily life now heavily depends on various electronic appliances, which are typically operated by one or more IC chips. Such chips are designated as System-on-Chips (SoCs) when they integrate a CPU and a set of peripheral modules. Due to the worldwide strong momentum to pursue green technology, low energy has become a key requirement for modern SoCs. In this work, we developed an energy modeling...
Due to the continuous shrinking of the transistor sizes which is strongly driven by Moore's law, reliability becomes a dominant design challenge for embedded systems. Reliability problems arise from permanent errors due to manufacturing, process variations, aging as well as soft errors. As a result, the hardware will consist of unreliable components and hence, the development of embedded systems has...
In this paper we develop a hybrid supervisory control architecture in a real-time environment for constrained nonlinear systems. The strategy is based on Command Governor (CG) ideas that are here specialized in order to take into account both time-varying set-points and constraints. Experimental results on a laboratory four-tank test-bed are presented.
Prototype Fast Breeder Reactor (PFBR) is a mixed oxide fuelled, sodium cooled, 500 MWe, pool type fast breeder reactor under construction at Kalpakkam, India. The reactor core consists of fuel pins assembled in a number of hexagonal shaped, vertically stacked SubAssemblies (SA). Sodium flows from the bottom of the SAs, takes heat from the fission reaction, comes out through the top. Reactor protection...
Recent work in the FPGA acceleration of molecular dynamics simulation has shown that including on-the-fly neighbor list calculation (particle filtering) in the device has the potential for an 80× per core speed-up over the CPU-based reference code and so to make the approach competitive with other computing technologies. In this paper we report on progress and challenges in advancing this work towards...
One of the main goals of E-UTRAN is to provide seamless access to voice and multimedia services with strict delay requirements, which is achieved by supporting handover from source cell to target cell. Proper handover algorithms can make the system increased capacity, better coverage, higher throughput, reduced latency requirements. In this paper we give an overview of the LTE intra-access handover...
The design of new architectures can be simplified with the use of retargetable instruction set simulation tools, which can validate the decisions in the design exploration cycle with high flexibility and reduced cost. The increasing system complexity makes the traditional approach to simulation inefficient for today's architectures. The compiled simulation technique makes use of a priori knowledge...
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