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Closed-form expressions of the parasitic insulator capacitance and the substrate capacitance for tapered through-silicon vias (T-TSVs) are proposed. The expressions are suitable for TSVs with high aspect ratio (thin and long). The maximum percentage errors between the calculated and simulated results for the insulator capacitance and the substrate capacitance are 1.86% and 3.75%, respectively. Then...
Engineering change orders (ECOs), which are used to apply late-stage specification changes and bug fixes, have become an important part of the field-programmable gate array design flow. ECOs are beneficial since they are applied directly to a placed-and-routed netlist which preserves most of the engineering effort invested previously. Unfortunately, designers often apply ECOs in a manual fashion which...
The emergence of multicore and many-core processors has introduced new opportunities and challenges to electronic design automation research and development. While the availability of increasing parallel computing power holds new promise to address many challenges in computer-aided design (CAD), the leverage of hardware parallelism can only be possible with a new generation of parallel CAD applications...
Active filters are known as the best tools for harmonic mitigation as well as reactive power compensation, load balancing, voltage regulation, and voltage flicker regulation on the power lines. To introduce the operation of active filters in education, it is a good method to use a software, named SPICE. It is a good choice, because it has a high level of objects for simulation, and good presentation...
In this paper, we propose a novel unipolar CMOS device with embedded oxide. Good inverter and logic gate output waveforms and behaviors are obtained. Utilizing the punch through effect, the Non-Classical Unipolar CMOS is demonstrated to enhance the tPLH so that the average delay time can be improved 23% when compared with the conventional CMOS. Due to all NMOS structures are only exploited and the...
This paper presents an implemented 4-bit phase ADC circuit. It introduces a model to calculate its dynamic range considering second order effects including non-linearity and offsets. The study also encompasses the phase resolution and validates the model with measurement results from the implemented chip. Our analysis shows that the phase ADC is extremely robust against circuit non-idealities and...
Silicon-controlled rectifier (SCR) has been reported with the good electrostatic discharge (ESD) robustness under the lower parasitic capacitance among ESD devices in CMOS technology. To correctly predict the performances of SCR-based ESD-protected RF circuit, it is essential for RF circuit design with accurate model of SCR device. The small-signal model of SCR in RF frequency band is proposed in...
NoC (Network on Chip) is an emerging paradigm for design of VLSI/ULSI circuits to overcome communication bottleneck of traditional bus based systems. NoC communication framework consists of regularly placed routers, which are connected to processing cores. NoC performance is determined by latency and throughput for communication requirements. NoC communication traffic modelling plays an important...
In this work, we explore the effects of the number of fins and fin structure on the device DC, dynamic behaviors, and random-dopant-induced characteristic fluctuations of multifin field effect transistor (FET) circuits. Multifin FETs with different fin aspect ratios [AR ≡ fin height (Hfin)/fin width (Wfin)] and a fixed channel volume are simulated in a three-dimensional device simulation and the simulation...
The aim of the presented work is to improve the quality of testing of SoC digital cores surrounded with test wrappers. The paper presents a new effective delay fault test generation method for the transition faults based on the skewed-load test. The generated delay fault test can be applied to a SoC core through a test wrapper architecture with only a simple boundary scan chain. This eliminates the...
Due to increasing integration densities and the emergence of nanotechnology, especially reliability and power related design aspects become critical for chip design. Since the arising problems are enforced by high circuit temperatures, the need for a possibility to model thermal behavior of a system in an accurate and physically correct way becomes inevitable. Hence, in this paper VulcaNoCs, a SystemC-based...
Based on the background of battery charging system, in this paper, the small-signal equivalent circuit model of phase-shifted full-bridge ZVS DC/DC converter is established, then its transfer function is derived, and a single closed-loop voltage-mode controller is designed. In order to analyze anti-grid voltage disturbance capacity, transfer function of audio susceptibility is presented, and the anti-grid...
In this paper, we proposed a new car following model based on the Full Velocity Difference (FVD) model, with the acceleration of the front car considered. Compared with the FVD model, the improved model can simulate the motions of cars starting from a traffic signal more nature. Numerical simulation results show that the stability of the improved model is better than the FVD model, with appropriate...
This paper presents an analysis on energy dissipation of a digital half band filters operated in the the sub-threshold (sub-VT ) region with throughput constraints. The degradation of speed in the sub-VT domain is counteracted by unfolding the architectures. A filter is implemented in a basic 12-bit and its various unfolded structures. The designs are synthesized in a 65 nm low-leakage high-threshold...
A serious highway accident with long duration will lead to a great delay. If the extended travel time is beyond travelers' tolerance, they will make a detour by choosing any other roads. However, the driver's behavior of taking other routes will make an impact on the surrounding road network. Thus that impact is called the indirect impact by highway traffic accidents in road network. The range of...
On-chip power supply noise has become a bottleneck in 3D ICs as scaling of the supply network impedance has not been kept up with increasing device densities and operating currents with each technology node due to limited wire resources. In this paper we proposed an efficient and accurate model to estimate peak-to-peak switching noise, caused by simultaneous switching of logic loads along a vertical...
In this Letter, we discuss delayed Hopfield neural networks of variable coefficients and distribution, based on globally Lipchitz continuous activation functions, the equilibrium point and the Lyapunov functional method. Sufficient conditions ensuring Globally Asymptotical Stability of neural networks are given.
A single-chip microcomputer-based test device of flash relay is presented in this paper, whose circuit and testing method are also introduced. The test device can not only detect parameters of relays in dynamic process, but also has additional functions such as durability detection, failure indication and so on. Finally, a simulated load circuit aiming at improving the test environment is designed,...
This work describes a novel modeling and simulation approach of brushless DC motor control system depended on analysis of it's mathematical model. The brushless DC motor ontology model, the voltage type inverter circuit model, the hysteresis current tracking comparative model and the PID speed controller model were constructed in the Simulink environment of Matlab. S-function was used in modeling...
A strain of Citrobacter freundii with sulfate-reducing function was isolated from the sticky mud at the bottom of cooling tower in a power plant. Scanning electron microscopy (SEM) was applicated to observe the cell morphology in recycled water and the medium; the sizes of cells found in reclaimed water were slightly larger than in the medium. Growth curves showed that generation of the strain were...
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