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Voltage Balance of the series-connected dc-link capacitors is the key problem of three-level diode-clamped converters. In this paper, an auxiliary voltage balance circuit (VBC) is presented to maintain the voltage balance of dc-link capacitors. The voltage balance circuit consists of a clamping capacitor and a current-limiting inductor. With the clamping capacitor, the voltage stresses of the auxiliary...
Negative bias temperature instabilities in commercial IRF9520 p-channel power VDMOSFETs under both static and pulsed bias stress conditions were studied. The pulsed voltage stressing caused generally lower shifts as compared to static stressing performed at the same temperature with equal stress voltage magnitude, as a consequence of partial recovery during the low level of pulsed gate voltage. Furthermore,...
A reliability study under high RF power stressing was conducted on two SiGe cascode Low Noise Amplifiers (LNA) using an in-house reliability tool. The first LNA was stressed at 19 dBm of RF power during 600 hours. Obtained results (relative degradation values in dB) showed a decrease of 11% in the small-signal gain (S21), while the second was stressed at 20 dBm of RF power during non-stop 600 hours...
In this contribution, impact of extreme environmental conditions in terms of energy-level radiation of protons on SiGe integrated circuits is experimentally studied. Canonical representative structures including linear (passive interconnects/antennas) and non-linear (Low Noise Amplifiers) are used as carriers for assessing impact of aggressive stress conditions on their performances. Perspectives...
The lifetime of power DMOS devices subjected to Thermal Induced Plastic Metal Deformation (TPMD) is highly dependent on the design of the metallization systems and thus requires the understanding of temperature, stress and strain distribution. This paper introduces and studies via numerical simulations with finite element method (FEM) a simple three dimensional (3D) transistor substructure commonly...
A compact aging model for circuit simulation has been developed by considering all possible trapped carriers within MOSFETs. The hot carrier effect and the N(P)BTI effect are modeled by integrating the substrate current as well as the oxide field change due to the trapped carriers. Additionally, the carriers trapped within the highly resistive drift region are included for high-voltage (HV)-MOSFET...
In this work, a previous software used to simulate partial discharges (PDs) under Alternating Current (AC) stress has been modified in order to evaluate the PDs behavior under a voltage stress close to the Direct Current (DC) waveform. By using a full-wave and a half-wave rectifier, the specimen with an air void defects has been subjected to a gradual constant stress. Finally, a capacitive filter...
The simulation of aging induced degradation mechanisms is a challenging task during the design of digital systems. Parametrical degradations can be handled most accurately at TCAD level, as the physical models like [1] and [2] can be implemented directly. On the other hand, timing failures caused by such degradations cannot be assessed exactly lower than Register Transfer Level (RTL), where the notion...
This paper presents an analysis of the bias temperature instability (BTI) induced pulse broadening of single event transients (SETs) in inverter chains. A novel deterministic simulation methodology for BTI, using the trapping/de-trapping framework, is proposed and implemented in a commercial SPICE tool. The developed simulator properly predicts the possibility that an SET pulse may suffer propagation-induced...
Testing and debugging of electrostatic discharge (ESD) or electrical fast transient (EFT) issues in modern electronic systems can be challenging. The following paper describes the design of an on-chip circuit which detects and stores the occurrence of a fast transient stress event at the ESD protection structures in an I/O pad. Measurements and simulations of a test circuit in 90 nm technology show...
A SPICE-level aging simulation methodology is developed to predict the NBTI degradation in short term and long term region. This methodology enables 10 years NBTI aging prediction under any bias conditions (including stress and recovery) by completing the time-tracing and extrapolation procedures in a single step. The proposed methodology significantly improves the speed of the long term simulation...
A failure analysis of a product due to the on chip ESD structure defects is presented in this paper. ESD is one of the most important reliability issues in the design of integrated circuits. About 40% of the failure of integrated circuits is related to ESD/EOS stress. In order to improve the reliability of ICs, the design of ESD protection is increasingly necessary for the modern semiconductor industry...
Modeling the negative bias temperature instability (NBTI) can optimize circuit design. Several models have been proposed and all of them can fit test data well. These models are extracted typically by fitting short accelerated stress data. Their capability to predict NBTI aging outside the test range has not been fully demonstrated. This predictive capability for long term aging under low operation...
The feature size of integrated circuit devices continues to decrease. And with the development of metal interconnection technology, metal wire constantly changes to thin and thin such that metal resistance increase, current density rise and the heat generated augment. For these reasons the integrated circuit reliability about electro-migration (EM) declines which is a serious threat to IC's performance...
This paper proposes a high-efficiency single-phase three-level bidirectional inverter. The proposed inverter has a three-level power switching circuit. It can reduce switch voltage stresses with low harmonic components. It has common-mode capacitors at the ac-filter to suppress the ground leakage current for high power quality. Its circuit operation and control strategy are described. Its common-mode...
An effective optimization approach for the electromigration (EM) reliability in power grid (PG) has been presented in this paper. With core technology development and the key feature size of integrated circuits decreasing, it is more serious for the EM-induced failure occurrence in the entire PG. However, previous PG studies focus on supply noise optimization and neglect the EM influence in lines,...
Variability and degradation in RRAM devices involve complex physical mechanisms that depend on the device, environment and programming/read operation. The development of solid and accurate compact models, ready to be used in standard circuit simulators, requires the meticulous emulation of this kind of non-ideal effects. In this work we present an advanced approach for the emulation of complex variability...
This paper presents a toolbox for the automation of the electrical characterization of CMOS transistors. The developed software provides a user-friendly interface to carry out different tests to evaluate time-zero (i.e., process) and time-dependent variability in CMOS devices. Also, the software incorporates a post-processing capability that allows users to visualize the data. Moreover, without loss...
The availability and efficiency of reliability simulators for analog ICs is becoming critical with the scaling of devices down to the nanometer nodes. Two of the main challenges here are how to simultaneously include different sources of unreliability (such as the time-zero or spatial variability and the aging or time-dependent variability), and how to account for the self-induced changes in device...
The operating characteristics and protection against electrostatic discharge (ESD) offered by a protection device when implemented in a real circuit may differ from those suggested via a circuit simulation, particularly at the system level. We assumed that this can be partly attributed to the failure of the snapback characteristics to account for the frequency responses of the pass and reflection...
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