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For the first time, a scalable load balanced Birkhoff-von Neumann TDM switch IC with SERDES interface circuits for high speed networking applications was implemented. Any NtimesN Birkhoff-von Neumann TDM switch could be constructed recursively from the designed TDM switch IC to achieve switching capacity of hundred gigabits per second or higher. The TDM switch IC contained a digital 8times8 TDM switch...
A 0.18mum CMOS 2.4GHz LNA (low noise amplifier) with digitally switchable capacitance has been designed to investigate its ability to compensate for performance variation across worst case process conditions. The effects of transistor model and passive component variation are first simulated to quantify the range of performance uncertainty. The use of various methods of switchable capacitance is then...
Employing multiple supply voltages (multi-VDD) is attractive for reducing the power consumption without sacrificing the speed of an integrated circuit (IC). In order to transfer signals among the circuits operating at different voltage levels specialized voltage interface circuits are required. Two novel multi-threshold voltage (multi-Vth) level converters are proposed in this paper. The proposed...
This paper presents the design of a 12 Gbps multi-lane 231 - 1 pseudo-random binary sequence (PRBS) generator in 0.18 mum TSMC process. The design incorporates a traditional CMOS latch optimized to operate at frequencies close to the ft of the process. In order to operate at frequencies higher than the limit imposed by the ft of the PMOS devices, the PRBS uses current-mode logic (CML) multiplexers...
Design and verification of a low-voltage, low-power, and extremely small area successive approximation registered analog-to-digital converter (SARADC) for sensor network applications are presented. The 8-bit SARADC employed a capacitor-based hybrid digital-to-analog converter and a simplified digital control block to achieve low power consumption and small area and a charge pumped switch to reduce...
The implementation of a 0.18μm CMOS 2.1GHz sub-sampling receiver front end with fully integrated fourth-and second- order Q-enhanced LC filters is described. The use of an integrated fourth-order filter allows the amount of noise aliasing due to sub-sampling to be reduced and the bandwidth and roll-off factor to be independently controlled. When tuned to a high effective quality factor of 210, the...
A low power ultra-wideband (UWB) common-gate low noise amplifier (CGLNA) for IEEE 802.15.3a is presented. In order to save the power consumption, a current-reuse technology is used. For extending the bandwidth, the proposed circuit uses and the stagger tuning technique of two stacked stages with different resonant frequencies. The circuit is simulated with TSMC 0.18 mum mixed signal/RF CMOS process...
A 2.5Gb/s burst-mode limiting amplifier for gigabit passive optical networks (GPON) is presented in this paper. A multistage architecture with a feedforward automatic threshold control (ATC) circuit is used for quick response. A response time of 5ns and sensitivity of 4 mVpp1 is achieved by introducing a modified ATC circuit and a modified amplified stage with active feedback and negative Miller capacitance...
A low power CMOS voltage reference circuit was designed and implemented by TSMC 0.18-mum CMOS process. The voltage reference circuit uses the VGS difference between two MOSFETs operating in the weak-inversion region to generate the voltage with positive temperature coefficient. The reference voltage can be obtained by combining the weighted VGS difference with weak-inversion VGS voltage, which has...
In this paper, capabilities of switched-current (SI) circuits are utilized to design a high-speed A/D converter. New methods to improve the performance of the SI circuits are introduced. An 8-bit 300MS/s pipeline ADC is design in 0.18mum CMOS technology and an ENOB of 7.3b is obtained from simulations. The ADC consumes 40mW from a 1.8V supply.
This paper presents a low-voltage, reduced-area CMOS bandgap reference (BGR) circuit for low-power applications. Significant area reduction is achieved by utilizing a resistive T-network in combination with layout-efficient opamp compensation. A complete analysis, including the dual-loop stability, reveals several tradeoffs between area, loop-gain, stability and offset sensitivity. Based on this analysis,...
Context-based adaptive 2D-VLC (CA-2D-VLC) is adopted by AVS. In this paper, we present an area-efficient VLSI implementation of CA-2D-VLC decoder. Data compression storage (DCS) method is proposed in memory optimization for VLC tables and a reduction of 30% in on-chip memory cost is achieved. Furthermore, an Exp-Golomb decoder is developed with codeword segmentation decoding (CSD) method, which saves...
Ultra low power sensor node for wireless health monitoring system was designed and implemented in 0.18-mum CMOS. The sensor node functions as an interface circuit to both sensor and RF transceiver. The sensor node consists of an amplifier, an ADC (analog-to-digital converter) as well as digital system. The digital system is embedded with DSP (digital signal processing) for heart rate processing and...
A dual-slope PFD (phase-frequency detector)/CP (charge pump) frequency synthesizer architecture for reducing the settling time of the loop is presented in the paper, which can achieve automatic adjustment of the loop bandwidth and high spectral purity. An adaptive self-tuning algorithm is introduced to effectively enlarge the frequency tuning range in a low VCO gain, where the aim of the adaptive...
Squaring circuits are an important building block for impulse-radio UWB non-coherent receivers. This work proposes a squarer, based on the quadratic law of saturated transistors. Such a circuit has already been proposed for lower frequency applications, therefore this work focuses on the extension to ultra wide bandwidth, with particular care to the consequences related to the deviation from the ideal...
A new BPSK modulator for Bluetooth applications is presented. The proposed modulator minimizes the bandwidth of the modulated carrier by minimizing the degree of sharpness of the transactions of modulated carrier. To avoid the drawbacks of large silicon area requirement of passive spiral inductors and transformers, CMOS active transformers are developed from corresponding CMOS active inductors. They...
In this paper, a low-power high-speed static frequency divider is proposed. By utilizing the forward body-bias (FBB) technique and parallel switching topology which employ differential PMOS input pair, the proposed 2:1 static frequency divider can not only be operated at a supply voltage of 0.7V but also keep the structure of tail current source to provide constant current. The frequency divider is...
In this paper, we propose a new voltage controlled oscillator (VCO) with a high oscillation frequency yet low power consumption. The oscillator which is a single stage circuit has a low phase noise due to reduced noise sources. To evaluate the performance parameters, the oscillator was simulated in a 0.18-μm standard CMOS process. The results show that the oscillation frequency of VCO may vary between...
In this paper, the design and experimental results of the fully integrated CMOS current sensors and power sensors for RF built-in self-test (BIST) applications are presented. By utilizing a standard 0.18-mum CMOS process, a 5-GHz RF LNA incorporated with the on-chip sensors is fabricated for demonstration. With the proposed BIST technique, the circuit parameters of the LNA including the dc current,...
Improvement of diagnosis methodologies is a key factor for fast failure analysis and yield improvement. As bridging defects are a common defect type in CMOS circuits, diagnosing this class of defect becomes relevant for present and future technologies. Bridging defects cause two additional current components, the bridge and the downstream current. This work presents the effect of the downstream current...
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