We build up a finite element modeling (FEM) approach to analyze the thermal performance of collector‐up (C‐up) heterojunction bipolar transistor (HBTs) with a heat‐dissipation via configuration. Highly compact heat‐dissipation packaging structures of GaInP/GaAs C‐up HBTs have been designed and evaluated systematically. In this work, we devise the 2‐D and 3‐D models to simulate the actual devices and to investigate the temperature distribution behavior. Results from 2‐D model indicate that the large heat‐dissipation via configuration can be further reduced by 29% to meet the requirement of HBT‐based small high‐power amplifiers (HPAs) for the cellular phones. Furthermore, the demonstrated results show that the maximum temperature within the collector calculated from 3‐D model is lower than that from 2‐D model. In the 3‐D analysis, it is revealed that the configuration can be reduced by 32%. Therefore, thinning the heat‐dissipation via constructed underneath the GaInP/GaAs C‐up HBT should be helpful for miniaturization of HBT‐based HPAs in future mobile communication systems. Copyright © 2009 John Wiley & Sons, Ltd.