New techniques for controlling the gain of a programmable gain amplifier (PGA) using an eight-bit digital word has been proposed in this paper. The output taps of the R–2R ladder network feed just the two Gm stages through the switches controlled by three MSB bits of the control word. The parasitic capacitance at the different taps has been reduced and equalized making the bandwidth of the PGA wider and the gain error more uniform over the entire control span. Two current banks composed of 32 current sources plus a 10 µA dummy current source, controlled by the five LSB bits of the digital control word, determine the tail currents of the Gm stages to set the PGA gain precisely linear in dB. Dummy current sources, however, have no effect on the gain of the PGA, they will prevent the transistors from turning OFF making the gain update rate faster. A differential PGA has been designed in a 0.18 µm–1.8 V-CMOS technology. The maximum gain error is less than 0.03 dB in different corner cases. At the maximum gain, the bandwidth and the input referred noise voltage of the PGA are 82 MHz and 4.1 nV/√Hz respectively, while the circuit draws just 4.8 mA current from the supply.