This paper presents the design aspects of low power digital PLL. The performance determining parameters of a digital PLL are lock range, capture range, jitter in generated output signal and power consumption. Its performance is mainly governed by two building blocks namely the voltage controlled oscillator (VCO) and phase detector. We have performed the complete analysis of phase noise and power consumption of current starved VCO, a novel D flip-flop based phase detector and transmission gate based charge pump. We have introduced a charge pump which is giving a remarkable reduction in reference spur. As PLL is used for many applications like as a frequency synthesizer, for clock deskewing, for jitter reduction, in FM radios so everyone demands a low cost low power highly integrated PLL design. Best efforts have been made to design a MOSFET based low power, low cost GHz range digital PLL. The main objective of this paper is to design a low power digital PLL which produces a very stable clock signal having jitter less than 1ps, power consumption less than 805uw ,output frequency ranged from 0 to380MHz at a supply voltage of 1.8V.
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