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This paper presents a technique for the fault-based test of the analog amplifiers. The circuit defects are modeled with the 2-fault transistor models. The test method combines the amplifier evaluation both in and out of the normal operating region, with the transconductance of the amplifier being the key test parameter. Furthermore, the additional low current test is employed in order to maximize...
In the recent years, Approximate Computing (AxC) has emerged as a new paradigm for energy efficient design of Integrated Circuits (ICs). AxC is based on the intuitive observation that, while performing exact computation requires a high amount of resources, allowing a selective approximation or an occasional relaxation of the specifications can provide significant gains in area, performances and energy...
Management systems based on elementary relay background are ubiquitous within railways of endless Post Soviet Union expanse. The aforesaid systems considered as rather robust ones with provision of high level safety, which may solve the task reckoning contemporary rail stock transportation supervision. Hence, with actual speed enhance routine, being conducted on railway tracks, structural defects...
This paper presents the computational procedure of the most generalized version of the stabilized fast Recursive Least Squares (RLS) adaptive filtering algorithm. It is considered the algorithm for the adaptive filters with an unequal number of weights in channels. The using of the sliding window and dynamic regularization, when the correlation matrix is estimated, allows the algorithm to process...
This paper presents a framework to evaluate the error rate of a design implemented in an FPGA, depending on the operating conditions. The effects of the operating temperature as well as voltage variation are taken into account. For example, in applications such as the electric vehicle motor control, the non-negligible electromagnetic field can result in FPGA supply voltage variation. It is shown that...
The article covers the issues of the synthesis of self-checking discrete systems. The authors introduced the method of building modified codes with summation of weighted transitions between the bits taking neighboring positions in data vectors. The new codes with summation possess the same number of check bits as classical Berger codes, but detect more errors in data vectors. Modified codes with summation...
In this paper we investigate how different randomization approaches influence the success of horizontal DPA attacks. We use our own ECC design to run the experiments. We applied the following randomization techniques: EC point blinding, key randomization and a combination of both. Our experiments demonstrate the fact that these well-known randomizations of processed data are not effective against...
A detailed analysis of error controlled divisible codes' building techniques was carried out, aimed at error detection in data vectors, which relate to summation codes' class. Summation codes classification was suggested, covering the whole diversity of modification methods of the existing classical and modular summation codes. New methods of summation codes modification were specified making it possible...
In this work features of measurement, processing and analysis of electrical characteristics of MOSFET's subjected to various kinds of static irradiation (neutron, electron, and y-rays) and temperature in the extended high/low ranges are analyzed. As a result a unified (with account for radiation and temperature) automated measurement, parameters extraction and modeling system is developed, which presents...
This paper contains an analysis of the payload of the popular ransomware for Windows, Android, Linux, and MacOSX platforms. Namely, VaultCrypt (CrypVault), TeslaCrypt, NanoLocker, Trojan-Ransom.Linux.Cryptor, Android Simplelocker, OSX/KeRanger-A, WannaCry, Petya, NotPetya, Cerber, Spora, Serpent ransomware were put under the microscope. A set of characteristics was proposed to be used for the analysis...
The combined Electro-Thermo-Rad models were developed for SPICE simulation of hardened SOI/SOS CMOS ICs for aero-space applications. They account for thermal (low, high temperature, selfheating) and radiation effects (total dose, particles fluence, single heavy particles, transient ionizing radiation effects) in SPICE model of MOSFET fabricated with SOI/SOS semiconductor technologies. The models were...
The smart cloud traffic light sequencer, focused on optimal control of traffic flows at the crossroads, is proposed within the framework of creating cloud traffic control [1]. A logical architecture of the sequencer free of arithmetic operations, intended for generating control signals, depending on the number of cars on intersecting lines. The ways of increasing the traffic capacity of intersections...
Characteristics of codes with summation of unit data bits are analyzed, the latter are often applied in technical diagnostics of discrete systems' problems. The contributors of the article suggest a fundamentally new method of summation code modification, based on decomposition of data vectors' digits, the formation of new vectors, weight estimation and writing down the obtained figures in corresponding...
The article proposes a new approach for organization of concurrent error detection (CED) systems of combinational logic circuits. This approach implies the implementation of combinational circuit layout analysis, as well as consideration of the features of separable codes with higher error detection performance for errors with low multiplicities. CED system supposed to be built based on division the...
In this paper we propose a novel CNN hardware accelerator, called AlScale, capable of accelerating convolutional, pooling, fully-connected and adding CNN layers. In contrast to most existing solutions, AIScale offers a complete solution to the full CNN acceleration. AIScale is designed as a coarse-grained reconfigurable architecture, which uses rapid, dynamic reconfiguration during the CNN layer processing...
Authors describe firstly obtained necessary and sufficient conditions for detection of a logic component output fault in the combination logic structure controlled on the basis of Berger code. It is demonstrated that for the solution of the given task not only Berger code property of identifying any unidirectional errors in data vectors, but also the property of any asymmetric errors detection may...
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