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In this paper, the total ionizing dose effects on electrostatic discharge (ESD) protection devices are investigated. Irradiation is conducted with 1.5 MeV He+ from a RPEA 4.0 MV Dynamitron accelerator, and the Barth 4002 transmission line pulse (TLP) tester is used for measurements. The ESD devices considered are a P+/NW diode, a Zener diode, gate grounded NMOS (GGNMOS), and lateral silicon controlled...
We have developed a new method to quantitatively evaluate the detectability for voids in bonded wafers by using ultrasonic inspection. The test sample for evaluation consists of bonded two Si wafers and has artificial voids between the wafers. The depths of these artificial voids are 5, 10, 20, and 170 nm. In this study, the evaluation was made by obtaining the images of artificial voids by using...
Large scale and high density packaging of ASICs are usually achieved by FCBGA forms. The structure and materials are more complicated in FCBGA, which would cause reliability concerns in situations where thermo-mechanical stressing is dominant. Accelerated temperature cycling reliability test was performed on 90-nm/8-level copper based FCBGA packaging devices, and open failures dominated by thermo-mechanical...
In this study, we investigate the Ron degradation in D-mode AlGaN/GaN MIS-HEMTs on a Si substrate via an accelerated step stress at different temperatures. We have observed a three-phase Ron degradation behavior, which is highly correlated with a drain bias and back gate bias. First, the Ron degradation increases till a peak value when the drain bias increases. Second, when the drain bias increases...
Although nano-particles have attracted extensive studies in material science and technology for decades, how to measure the particle size efficiently and conveniently still remains to be a problem unsolved. In this paper, Si nano-particles prepared by annealing a very thin amorphous Si layer were inspected by atomic force microscopy (AFM) as well as SEM and TEM e-beam techniques. Results extracted...
In this paper, an improved LDPMOS_SCR without a LDPMOS structure (NonLDPMOS_SCR) is discussed, which is realized in 0.5-μm 5V/18V/24V CDMOS process. The theoretical analysis and transmission line pulse (TLP) testing system are used to predict and characterize the proposed ESD protection devices. According to the measurement results, compared with the normal LDPMOS_SCR, NonLDPMOS_SCR elevates the second...
Based on Meridian system, failure analysis of an advanced process LCD driver IC were conducted using laser voltage probing (LVP) and dynamic laser stimulation (DLS) techniques. The results demonstrate that LVP technique can effectively track cell transmission signal and intensity, and that failed location can be further identified accurately by using DLS technique followed by layout circuit analysis.
A failure analysis of a product due to the on chip ESD structure defects is presented in this paper. ESD is one of the most important reliability issues in the design of integrated circuits. About 40% of the failure of integrated circuits is related to ESD/EOS stress. In order to improve the reliability of ICs, the design of ESD protection is increasingly necessary for the modern semiconductor industry...
A theory has been developed for geometric variation of trigate FinFETs. This geometric variation includes both line roughness induced variation and oxide-thickness variation, which can be measured from gate capacitance and Ig current variations, respectively. Experimental results show that trigate devices are subject to serious line variations as the fin height scales up and the fin-width scales down,...
3D-IC has been recognized as one of the technology solutions from More than Moore. Xilinx's 3D-IC FPGA has been well adopted by the industry since the first Virtex®-7 2000T introduced in 2011. In particular recently, data center requires large volume of 3D-IC for its applications. To fulfill the high demand effectively the best way is to provide the high yield and reliability 3D-IC product supply...
This paper highlights systematic fault isolation approaches to identify back-end of line metal bridging through the combination of techniques such as photon emission, soft defect localization, laser voltage probing as well as combinational logic analysis, to successfully pin point a single metal layer for physical failure analysis, thus boosting the overall success rate and turnaround time.
SRAM is a major component in semiconductor industry which often requires extensive and exhaustive method of fault isolation, especially for a non-visual defect in a soft failure mode. For these cases, nanoprobing on CA layer is often performed but there are times when it fails to isolate any defect. One reason may be because the failure only occurs at high temperature test environment. This paper...
Corrosion on wafer level aluminium-copper (Al-Cu) interconnects and electroless nickel-palladium (Ni-Pd) pads were characterized using inline metrology and physical failure analysis methods. Chemical methods were then used to study the mechanism of the defects. Al-Cu localized corrosion occurred as Al-oxides growth with the presence of fluorine (F) and chlorine (Cl) due to moisture stain. Using chemical...
In this paper, analysis of the gate recess variation on DC and RF characteristics on 0.25um psuedomorphic high electron mobility transistor using Sentaurus TCAD simulation have been carried out. Hydrodynamic transport model have been employed for the simulation. Furthermore, off state breakdown characteristics are also exploited, while exploring the essential features of 2-dimensional electron gas...
In this paper, we present the experimental I-V and C-V characterization of vertical trench DMOS with different gate electrode recess depths. NBTI/PBTI test, via static bias stress test method was also performed in order to identify possible contaminations of the channel region. Effects of increasing this recess depth on the main electrical and capacitance performances are accurately measured. We concluded...
In this work, the high temperature (up to 375°C) dynamic characteristics of 1.2kV SiC VDMOS, including the gate charge, the switching and the body diode reverse recovery characteristics, are measured and analyzed in detail. The experiments show that, with the increase of temperature, the Miller plateau declines, the reverse recovery charge rises, the turn-on time decreases and the turn-off time increases...
In this study, we implemented the backside PLS (Photoelectric Laser Stimulation) based circuit edit on an analog circuit block of a mixed-signal IC (Integrated Circuit). In this technique, a laser with the wavelength in the NIR (Near Infrared) range is employed to optically stimulate the DUT (Device under Test) at the transistor level, and impact optically its electrical performance including threshold...
Novel 3D architecture of electronics packages raises immense challenges for electrical fault isolation and physical failure analysis (PFA). This paper describes a streamlined workflow involving 3D X-ray Microscopy (XRM) to effectively bridge fault isolation and physical failure analysis (PFA). The case studies on chip-to-chip micro-bump interconnecting failure will be discussed. X-ray microscopy improved...
Failure analysis is being performed in order to improve performance and stability of semiconductor devices. It is often required to detect and locate the failure without mold decapsulation. Conventional PEM(Photo Emission Microscope) and IR-OBIRCH (InfraRed Optical Beam Induced Resistance CHange)do not detect signal in package state because both the emission light and the stimulation light for IR-OBIRCH...
In this paper, we report a novel method of multi-location cross-section sample preparation for TEM failure analysis from the same planar view TEM sample, which is a large soft fail area. With the development of semiconductor technology, the sizes of devices are smaller and smaller, and the complexity of their structures is increasing. Though a test may show that a large area including multiple devices...
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