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This paper describes the use of Lock-In Thermography (LIT) technique to determine the defect Z-depth in flip chip. An empirical phase shift versus applied lock-in frequency plot for Flip-chip is first created by using samples with known defect Z-depth. The actual experimental phase shift data from reject samples with unknown defect locations are then measured and compared against the empirical phase...
A back-side grinding CMOS-MEMS process is well established for thinning wafers down to tens of micrometres for use in stacking chips. As a result of the mechanical process, the wafer backside is compressively stressed. In this paper, authors investigate the influence of the backside induced stress in MEMS/CMOS wafers thinned down to 35∼275 μm by means of a micro-Raman technique. We found that the...
RF Power amplifier often demands Zero-defect in application. However, it sees non-uniform stress during application. The time depend stress level depends on the input signals. This paper presents a way to predict the gate oxide lifetime, not only for the intrinsic oxide breakdown, but also for the extrinsic oxide breakdown. An appropriate gate oxide screening condition would enable the desired quality...
An investigation of radiated reliability of HBT and MOSFET which fabricated on 0.35 μm SiGe BiCMOS technology is presented under dose rates of 500 mGy(Si)/s and 1 mGy(Si)/s with a 60Co γ irradiation source. Gummel characteristics of SiGe HBT and transfer characteristics of MOSFET are measured before and after irradiation. Base current (IB), leakage current (IOFF) and threshold voltage (VTH) are extracted...
Thermal effects of the Tm:YAP crystal and the ZGP crystal that used in 5W Mid-infrared solid-state laser are the important factor which affects the laser output characteristic and the reliability. Starting with the thermal conduction function, Tm:YAP and ZGP crystals thermal effects simulation models are build by using finite element simulation technology, the numerical value of the highest temperature...
In this paper, a novel signal toggling technique in Electrical Optical Frequency Mapping/ Phase Mapping (EOFM/EOPM) and Electrical Optical probing (EOF) are performed to successfully localized the fault location and identify the physical defect promptly. A function square wave is asserted into the pin of interest, i.e. leakage pin or the function power pin, for EOFM and EOF purposes. This technique...
Zynq System-on-Chip (SoC) integrates both Processor and Programmable Logic architectures, where the whole functionality of a system is placed on a single chip. Due to the advancement of process technology, the complexity of circuit analysis becomes harder and the failure modes are becoming marginal, e.g., leakage in nano-ampere range. SoC devices require very challenging work for failure localization...
Laser voltage imaging (LVI) and laser voltage probing (LVP) are laser stimulation techniques to verify a device under test (DUT) and have been widely used for scan chain circuit debugging and various frequency-dependent failure modes. In the case of complex logic failures in advanced technology nodes, defect localization continues to be a challenge in the failure analysis field. Dynamic electrical...
This paper demonstrates integration non-destructive analysis tools solution of MEMS multi-bonding to inspect the fusion bonding interface and eutectic bonding interface to locate defect layers. This analytical study shows successful SAT (Scanning Acoustic Tomography) and IROM (Infrared Optical microscopy) inspection of MEMS multi-bonding single issue layer. The multi-bonding double layers were happened...
This study investigates the bias temperature instability in high-k/metal-gate pMOSFETs with a TiN barrier layer sandwiched between the metal gate electrode and HfO2 dielectric and for reliability improvement of such devices. The experimental results clearly demonstrated that the diffusion mechanism of oxygen and nitrogen resulting from the post metallization treatment was the root cause of bias temperature...
Segmentation technique for optimizing the holding voltage of SCR is discussed and implemented in a 0.6μm SOI process. Based on the prior researches, the holding voltage of SCR is a key parameter for latch-up risk assessment. The segmented SCR with external resistor paralleled with the parasitic Ptub resistor is proposed by modifying the layout, and the holding voltage can be increased. The TLP characterization...
In this study, impact of traps located at SiO2/Si interface on the time-dependent dielectric breakdown (TDDB) lifetime is investigated by modeling the Weibull distribution in high-k (HK) dielectric stacks. The results show that the interface traps will cause the distortion of Weibull slope of TDDB lifetime, decreasing the growing rate of the probability of breakdown after a long time.
In this study, a comparison of the interfacial adhesion strength of Plasma Enhanced Chemical Vapor Deposition (PECVD) silicon nitride (SiN)/Cu and High-Density Plasma Chemical Vapor Deposition (HDP CVD) SiN/Cu was performed using the 4-Point-Bending (4PB) technique. Differences in critical energy release rate value Gc, which is an indicator of the interfacial adhesion strength, were observed. The...
In this study, we compared the basic switching behaviors of HfO2, Al2O3 and HfAlOx (Hf:Al=9:1) based RRAM with Ti top electrode by setting various compliance currents (1mA, 5mA, 10mA, 15mA). The resistance ratio of HfO2 based RRAM (20 → 320) increases with compliance current whereas it drops not obviously for Al2O3 based RRAM (85→54). HfAlOx (Hf:Al=9:1)) based one has the best resistance ratio (300–440)...
In this paper, we studied the Al bondpad qualification methodologies and application in backend process optimization and improvement so as to provide good quality bondpads and wafers in wafer fabrication. The three Al bondpad qualification methodologies including OSAT, SLAT and Wafer Die Sawing Test were introduced and discussed.
The three-dimensional (3-D) NAND flash memory technology has been considered as a promising candidate for future memory solutions, because it overcomes the scaling limitation and reliability issues faced by conventional planar memory. Even though 3-D NAND flash memory structures have many merits, self-heating effect is aggravated seriously due to the poor thermal conductivity of some of the materials...
This paper reports a study of transient behaviors of diode-triggered silicon-controlled rectifier (DTSCR) electrostatic discharging (ESD) protection structures for ultra-fast Charged Device Model (CDM) ESD protection. The DTSCR ESD protection structures, fabricated in a 28nm CMOS process, were characterized using a new combined Very Fast Transmission Line Pulse (VFTLP) testing and TCAD simulation...
In this study, we found that inappropriate TU (top Cu metal line) geometry design induced product reliability failures issue. The TU geometry, having poor compatibility with wafer test probe issue, couldn't withstand the stress of wafer test probe resulting in fractures. Due to the inappropriate TU geometry design had major disadvantages in circuits characteristics. Reliability estimations exhibited...
NOR Flash life-time prediction is usually used by TTF calculation (ex. Vt Shift rate / read verify level / Istring variation etc). So by choosing different criteria and development processes will result in inconsistent product's time-to-failure (Fig1). This time we used the floating gate electrons concentration and temperature variation to calculate the EA(Fig2).
With process technology development and circuit density rapidly increases, shrinkage of semiconductor device geometries has become extremely difficult to effectively analyze defect. Therefore, an exactness failure analysis process flow and technique need to be considered in order to analyze the failure mechanism, especially complex failure analysis such as failure of open/floating signal net in logic...
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