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Transmission electron microscopy (TEM) is one of the most important characterization techniques in semiconductor failure analysis. However, preparation of a good TEM lamella for analysis has great challenges and requires a well-thought-out sequence of steps. The normal TEM sample preparation procedures, though time consuming, can fulfill majority of the sample requirements, but sometimes there are...
In this paper, a method to detect shorts at the gates of the storage node of a 6T SRAM bit cell via atomic force probing (AFP) at the Via 1 level is discussed. This method is useful for the preservation of physical evidence as well as to ease the probing operation due to the lower density and larger separations of vias compared to contacts. One particular case of single bit failure is documented,...
Wafer level chip scale package (WLCSP) devices have seen significant growth and demand in the recent years largely driven by the mobile consumer market. WLCSP offers significantly reduced package footprint, high electrical and thermal performance, and lower cost of manufacturing. After the initial qualification of the device, an ongoing reliability monitor program is critical in ensuring the continued...
Zynq System-on-Chip (SoC) integrates both Processor and Programmable Logic architectures, where the whole functionality of a system is placed on a single chip. Due to the advancement of process technology, the complexity of circuit analysis becomes harder and the failure modes are becoming marginal, e.g., leakage in nano-ampere range. SoC devices require very challenging work for failure localization...
Laser voltage imaging (LVI) and laser voltage probing (LVP) are laser stimulation techniques to verify a device under test (DUT) and have been widely used for scan chain circuit debugging and various frequency-dependent failure modes. In the case of complex logic failures in advanced technology nodes, defect localization continues to be a challenge in the failure analysis field. Dynamic electrical...
The three-dimensional (3-D) NAND flash memory technology has been considered as a promising candidate for future memory solutions, because it overcomes the scaling limitation and reliability issues faced by conventional planar memory. Even though 3-D NAND flash memory structures have many merits, self-heating effect is aggravated seriously due to the poor thermal conductivity of some of the materials...
In this study, we found that inappropriate TU (top Cu metal line) geometry design induced product reliability failures issue. The TU geometry, having poor compatibility with wafer test probe issue, couldn't withstand the stress of wafer test probe resulting in fractures. Due to the inappropriate TU geometry design had major disadvantages in circuits characteristics. Reliability estimations exhibited...
As the process of device is scaling down continually. Engineers are trying their best to challenge the limitations of physics in IC industry. However, power IC like power MOSFET and Insulated Gate Bipolar Transistor (IGBT) still have a high requirement despite device scale — downs. Here, we want to highlight a method to improve defect location in IGSS (Gate — Source leakage) failure, through this...
Failure analysis on static condition (static leakage and standby current level) failed device would not cost long time to find root cause, but dynamic functional failure will. Failure analysis with dynamic strategy to localize a failure point is more significant in complicated function failed IC (Integrated Circuit). This paper would present an efficient strategy to locate the defect using dynamic...
In this paper, Focus Ion Beam (FIB) 3-point localization method and its applications in Failure Analysis (FA) were introduced. The FIB capability of material milling plays an important role in FA, but sometimes the target site of milling is invisible in FIB, making it impossible to do specific cross sections. With the help of the proposed 3-point localization method, most invisible targeted sites...
This paper describes the case study of test method of gate source failure and the fault localization approach with aid of device physics theory. The nominal behaviour of IGBT device is turn on the moment gate voltage reaches the threshold voltage. However, in this case the device turn on before the gate voltage reaches to the ideal threshold voltage due to distracted by Gate-source capacitance. On...
Defect localization of short failures has been a big challenge in modern advanced nanoscale devices. In recent years, Electron Beam Induced Resistance Change (EBIRCh) technique has been applied to failure analysis. The EBIRCh technique incorporated into SEM based nanoprobing system allows not only direct electrical characterization of suspicious bridge sites but also direct pinpointing of short defects...
Electron beam absorbed current (EBAC) has been used to isolate defects in BEOL metal stacks. With the increasing layout complexity, metal signal lines often run over 100um area and over multiple metal stacks. This makes SEM inspections during polishing tedious, time consuming and easy to overlook the defect. With the EBAC technique, it often shows the entire routing of the signal line with additional...
This is a case study of an early failure analysis on a chip fabricated on the 40nm technology node. A large leakage current was observed in the high voltage (HV) supply after the chip was stressed as a part of an early failure rate (EFR) test. Electrical failure analysis (EFA) using Backside Emission spectroscopy [1] and Optical Beam Induced Resistance Change (OBIRcH) [2] showed the existence of hotspots,...
This paper highlights systematic fault isolation approaches to identify back-end of line metal bridging through the combination of techniques such as photon emission, soft defect localization, laser voltage probing as well as combinational logic analysis, to successfully pin point a single metal layer for physical failure analysis, thus boosting the overall success rate and turnaround time.
In wafer fabrication, it is important for analyst to be equipped with the mindset of deep dive towards uncovering the underlying “hidden and real” defect even after finding some anomaly that appears to be the root cause. This is critical as inexperience analyst may regards the 1st anomaly seen as the cause of the low yield issue and this will lead to wrong process fix by the process integration. In...
In view of reducing the process development cycle times with plausible time-to-market goals, it is of great demands to speed up the assessment pace, but at the same time not to jeopardize for the high level of quality requirements. Highly robust designs and process margins are the key differentiators and should be enforced in particular for the automotive markets. In this work, development of the...
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