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A novel electrostatic discharge (ESD) clamp circuit for power-rail ESD protection, consisting of the stacked transistors and biased RC network, is proposed in a 90 nm CMOS process. The biased RC network possesses a small footprint and the detection circuit has a pretty low leakage current of up to 12 nA under normal operation. The proposed ESD clamp circuit has a long hold-on time of 800 ns under...
An electrostatic discharge (ESD) protection design by using stacked diodes and silicon-controlled rectifier (SCR) as power clamp is presented to protect a K-band low-noise-amplifier in nanoscale CMOS process. Experimental results show that the proposed design can achieve higher ESD robustness without degrading the radio-frequency (RF) performance. Based on its good performances during ESD stress and...
Lack of accurate ESD device models and CAD methods makes on-chip ESD protection circuit design optimization and verification impossible. This paper reports a new circuit-level ESD protection simulation method using ESD behavior models to quantitatively analyze the ESD discharging functions at chip level, including checking the transient node voltage and branch current on a chip during ESD events....
A novel 2×VDD-tolerant electrostatic discharge (ESD) detection circuit which uses only low-voltage devices is proposed in a 0.18 um CMOS process. Under normal operating conditions, all the devices are free from over-stress voltage threat. Our proposed detection circuit achieves a high triggering efficiency with a much smaller footprint. Comparing with the RC based detection circuit, our proposed circuit...
ESD protection design for the RF transmit/receive switch (T/R switch) with embedded silicon-controlled rectifier (SCR) is proposed, where the SCR device is embedded in the ESD diode and the transistors of T/R switch by layout skill. Silicon chip verified in a 90-nm CMOS process has been measured by TLP and HBM ESD test to confirm its efficiency for ESD protection. The parasitic capacitance from the...
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