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To implement 8K Advanced BS receiver system, 8K HEVC decoder SoC is developed as key component. To solve the exceeded required memory bandwidth over physical memory bandwidth limitation issue for realizing 8K decoder, two types of multi-cast write back scheme, including reference data multi-cast write back and output data multi-cast write back, are introduced. 8K HEVC decoder chip is fabricated in...
A sparse spatio-temporal (ST) cognitive SoC is designed to extract ST features from videos for action classification and motion tracking. The SoC core is a sparse ST convolutional auto-encoder that implements recurrence using a 3-layer network. High sparsity is enforced in each layer of processing, reducing the complexity of ST convolution by two orders of magnitude and allowing all multiply-accumulates...
This paper presents a single-chip trinocular disparity estimation processor, capable of computing in real-time up to 2048×1080 resolution depth maps at 32fps with up to 256-pixel disparity range using two/three CMOS camera sensors. The most important feature of the presented design is that the chip is based on a trinocular adaptive window matching process that requires very limited on-chip memory,...
Data movement to and from off-chip memory dominates energy consumption in most video decoders, with DRAM accesses consuming 2.8x–6x more energy than the processing itself. We present a H.265/HEVC video decoder with embedded DRAM (eDRAM) as main memory. We propose the following techniques to optimize data movement and reduce the power consumption of eDRAM: 1) lossless compression is used to store reference...
This paper presents a SAR ADC using passive noise shaping and noise quantizer techniques. A ping-pong residue switching enables noise shaping at high sampling rate. The prototype in 14 nm achieves 69-dB SNDR at 25-MHz BW and 300 MS/s. The FOMs and FOMw are 169 dB and 20.5 fJ/conv.-step, respectively. With noise shaping only, the SNDR is 66.2 dB at 33-MHz BW and 400 MS/s.
This paper presents a low-power 2nd-order noise-shaping (NS) SAR ADC. Instead of using power-hungry op-amps, it uses switches and capacitors to make passive integrators for noise shaping. The overall architecture is simple and the NS order can be easily reconfigured from 0 to 2. A prototype chip is fabricated in a 40nm CMOS process. With 2nd-order NS, the chip consumes 143μW power at 1.1V and 8.4MS/s...
This paper presents a 510nW 12-bit 200kS/s SAR-assisted SAR ADC in 40nm CMOS at 0.7V supply. A re-switching technique is proposed to suppress DNL spikes so that the size of DAC capacitor array can be minimized to reduce switching energy. A set of 2-way charge pump is used to decrease settling time constant and to increase sampling linearity. The prototype ADC achieves the DNL/INL performance of 0...
This paper introduces an architecture and design for high resolution, high linearity Nyquist rate SAR ADCs requiring only a single simple calibration at startup. The proposed architecture benefits from an intrinsically linear 1.5 bit ΣΔ DAC to resolve the fine bits of the SAR ADC after a coarse conversion phase with a monotonically switched capacitive DAC. The ΣΔ DAC is also used for a single shot...
A 4.1Mpix 280fps stacked CMOS image sensor with array-parallel ADC architecture is developed for region control applications. The combination of an active reset scheme and frame correlated double sampling (CDS) operation cancels Vth variation of pixel amplifier transistors and kTC noise. The sensor utilizes a floating diffusion (FD) based back-illuminated (BI) global shutter (GS) pixel with 4.2e-rms...
To achieve better and faster material discrimination in applications like security inspection, X-Ray image sensors giving a highly resolved energy spectrum per pixel are required. In this paper, a new pixel architecture for spectral imaging is presented, exhibiting a 256 bin spectrum per pixel in a single image duration, up to two orders of magnitude higher than previous works. A prototype circuit,...
A low-noise global shutter (GS) CMOS image sensor (CIS) with two-stage charge transfer (2-CT) structure is presented. The low-noise wide dynamic range performance of the proposed pixel has been demonstrated by using column-parallel folding integration (FI)/cyclic ADCs. The GS image sensor with 5.6μm-pitch 1200 × 900 pixels is implemented with a 0.11 μm CIS technology. The noise and dynamic range are...
The required incorporation of an additional in-pixel retention node for global shutter complementary metal-oxide semiconductor (CMOS) image sensors means that achieving a large saturation signal presents a challenge. This paper reports a 3.875-μm pixel single exposure global shutter CMOS image sensor with an in-pixel pinned storage (PST) and a lateral-overflow integration capacitor (LOFIC), which...
An energy-efficient nonvolatile intelligent processor (NIP) is proposed for battery-less energy harvesting system. This NIP employs RRAM-based nonvolatile logics (NVL) with self-write-termination (SWT) scheme and low-power processing-in-memory (PIM) to achieve energy-efficient computing against frequent power-off situations. An NIP test chip was fabricated in 150nm CMOS process using HfO RRAM. This...
This paper proposes Recryptor, an energy efficient and compact ARM Cortex-M0 based reconfigurable cryptographic processor using in-memory computing. Recryptor is capable of accelerating a wide range of cryptography algorithms and standards, including public/private key cryptography and hash functions, by augmenting the memory of a commercial general purpose IoT processor resulting in a highly compact...
An ultra-light-weight PRINCE cryptographic processor is developed. A fully-unrolled differential-logic architecture saves delay, energy, and area (i.e. hardware weight) of XOR as a dominant cipher component. An S-box is composed only by four kinds of compact composite gates and a replica-delay-based transition-edge aligner prevents glitches accumulated in the long unrolled combinational-logic data...
This paper presents a strong silicon physically unclonable function (PUF) immune to machine learning (ML) attacks. The PUF, termed the subthreshold current array (SCA) PUF, is composed of a pair of two-dimensional transistor arrays and a low-offset comparator. The fabricated PUF chip allows 265 challenge-response pairs (CRPs) and achieves high reliability with average bit error rate (BER) of 5.8%...
Conventionally, SRAM PUFs are only used for chip ID. The proposed sequence dependent PUF expands the challenge-response space of an SRAM PUF by an order of rows(sequence length-1), making it suitable for authentication. In addition, it has a sequence dependent non-linear behavior making it more immune to machine learning attacks. In 28nm, the 64×64 SRAM-based PUF has a bit area of 388F2 with energy...
We present the first continuous-time digital IIR filter with power consumption tracking the input activity and varying by over 50×, resulting in a FoM varying from 2.5iJ to 0.05ÍJ. Only two tapped delays are used for a sixth-order filter. The 1.2 V 65nm CMOS prototype achieves very high stopband rejection and includes an output converter to synchronous mode, allowing integration with discrete-time...
A 300MS/s 12b SAR ADC achieving 61.6dB peak SNDR is presented. It reaches 60.5dB SNDR and 78.7dB SFDR with 0.8Vpp,diff input amplitude at Nyquist. The key elements are a comparator with inverter-based preamplifier and a SAR-based common-mode regulation. The regulation adjusts the common mode on a sample-by-sample basis to improve common-mode rejection. The ADC consumes 7.0mW from a single 0.85V supply,...
A 10-bit 2GS/s time-interleaved SAR ADC with low-complexity background timing skew calibration is presented. 10% of the area is utilized for the interleaving mismatch estimation and correction. The ADC achieves −64dB mismatch spur and 50.1dB SNDR at Nyquist rate, with 10.4mW power consumption and 0.014mm2 area in 16nm.
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