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The impact of strain and semiconductor/oxide interface traps (ITs) on the turn-on characteristics of a 10×10 nm2 nanowire (NW) Al0.05Ga0.95Sb/InAs heterojunction n-type tunnel field-effect transistor (TFETs) is carefully investigated using a full-quantum simulator. In order to capture the effect of traps on the device electrostatics in a way consistent with the ballistic approach, the SRH theory has...
The three-dimensional (3D) nature and continued dimensional scaling of Fin-, Nanowire-, and Gate-All-Around-FETs raise a host of unique challenges to device and process design that impact both performance and yield. We highlight selected technology challenges and solutions, specifically doping requirements for isolation, SD/E, and contact, as well as a new advanced planarization technique.
Germanium (Ge) is not a new material but now spotlighted for beyond Si-scaled CMOS. Ge p-MOSFETs have been well investigated and its high performance has so far been demonstrated. On the contrary, an achievement of high electron mobility Ge n-MOSFETs is quite challenging due to a large amount of interface states near the conduction band edge. So, we first discuss how to overcome “intrinsic challenges...
This review demonstrates the potential of low frequency noise diagnostics for the characterization of Ge-based and III–V technologies processed on a Si platform. The analysis of traps in both gate dielectrics and semiconductor films is illustrated for state-of-the-art devices.
In this paper, nanoscale germanium (Ge) fin etching with inductively coupled plasma (ICP) equipment by Cl2/BCl3/Ar gas is experimentally demonstrated. The impact of Cl2/BCl3/Ar gas ratio on etching induced Ge surface roughness, etch rate, sidewall steepness, uniformity and layout dependence are comprehensively investigated. The surface roughness is improved by increasing Ar flow rate. A nearly vertical...
The ultra-shallow NiGe/p+-Ge/n-Ge Schottky junctions with dopant segregation have been fabricated using Indium spin-on dopant and thermal diffusion, followed by NiGe growth with microwave annealing technique. The total junction depth of the NiGe/p+-Ge/n-Ge Schottky junction was scaled down to 9 nm, containing 6-nm-thick NiGe and 3-nm-thick p+-Ge region. It is found that the junction leakage current...
A possible strategy for the characterization of grown-in and processing-induced electrically active point and extended defects in high-mobility substrates is presented and illustrated by examples obtained on Ge as a prototype system.
This work demonstrates high-performance Ge p-channel metal-oxide-semiconductor field-effect transistors (PMOSFETs) [1] with ternary-phase NiGePt alloy Schottky source/drain (S/D) by low-temperature microwave-activated annealing (MWA) [2]. Process flow of Shcottky junctions is shown in Fig. 1. Interestingly, the formed NiGePt alloy is nearly single crystalline. We found the formation of ternary-phase...
Al2O3 films deposited as gate dielectrics on germanium (Ge) by atomic layer deposition (ALD) were post annealed in an ozone atmosphere at 450°C for 15, 25 and 35 minutes. The structure and chemical compound of Al2O3/Ge gate stacks were detected by X-ray photoelectron spectroscopy (XPS) measurements after ozone post annealing (OPA) treatments. It is confirmed by XPS measurements that this OPA treatment...
In this study, reactive-ion etching (RIE) of Ge in different ambient was systematically investigated. Several dominant parameters (applied power, gas flow rate and gas compositions) during the etching were considered to improve the profile of 3D Ge structures. Besides, it was experimentally confirmed that to obtain Ge sidewalls with small roughness and a large angle, adding O2 and an appropriate masking...
Advances in plasma process technology have contributed directly to advances in the miniaturization and integration of semiconductor devices. However, in semiconductor devices that encroach on the nanoscale domain, defects or damage can be caused by charged particles and ultraviolet rays emitted from the plasma, severely impairing the characteristics of nano-devices that have a larger surface than...
The concept of atomically controlled processing for group IV semiconductors is based on atomic-order surface reaction control. This approach is especially important for the epitaxial deposition of very thin (nm) layers. Here, the existences of Ge oxide in the CVD reactor resulting from former Ge deposition and hydrogen termination of the wafer surface is impacting the epitaxial growth essentially...
Accurate temperature monitoring of the silicon substrate remains to be a key issue for application of novel microwave annealing technology in advanced semiconductor processing. In this paper, a calibration system for temperature monitoring using infrared thermometer pyrometer is designed and temperature accuracy of silicon substrates with various doping concentrations is analyzed. Furthermore, an...
The hexagonally ordered patterns by self-assembly of block copolymer with diameter and spacing down to 23 nm and 15 nm, respectively, are capable of producing Si nanopores with high aspect ratio from patterned Au film. The etching feature size seriously depends on the block copolymer pattern template. The prepared nanostructure patterns were used as substrates for surface enhanced Raman spectroscopy...
A simple and effective method to grow GaN on Si substrates has been achieved. The method that GaN comes out from a submicron and deep hole with nearly zero dislocations above the mask is demonstrated. This work proves that reducing the epitaxy area by using mask and increasing the depth to width ratio of pattern contribute to filtering the dislocations and improving the quality of GaN.
Through-silicon via (TSV) induced stress field and device performance variation are investigated using N28 silicon data. Back-end-of-line (BEOL) dielectrics affects the stress field of via-last TSV. Asymmetric keep-out zone (KOZ) is observed, i.e. the absolute value of radial stress (|σr|) is different from that of tangential stress (|σθ|). The physics behind the asymmetry is described. A KOZ model...
This paper describes selected technologies for the 3D integration of MEMS devices. This comprises a Via Last approach for the formation of MEMS TSVs and a Cu based thermo-compression bonding method for the realization of small 3D-WLP devices. Moreover, the Aerosol Jet technique is discussed as method for the final assembly by means of printing conducting lines over 3D topography.
New 3D integration technology using self-assembly and Cu nano-pillar hybrid bonding are developed to achieve high-throughput and high-precision multichip-to-wafer stacking. Many known good dies (KGDs) are simultaneously self-assembled with a high alignment accuracy making use of liquid surface tension in a face-up configuration on a carrier wafer, called SAE (Self-Assembly and Electrostatic) carrier...
Based on a long-term investigation of material growth and fabrication procedure, the cryoHEMTs (Cryogenic High Electrons Mobility Transistors) made at the CNRS/C2N (formerly LPN) are now in the process to fill the gap of the FET (Filed-Effet Transistor) for high impedance, low-power and low-frequency deep cryogenic readout electronics. Different input capacitance cryoHEMTs have been fabricated and...
Trapping effects still limit the application of GaN-based high-electron mobility transistors (HEMTs). This paper further characters traps in GaN HEMTs based on the drain current transients. A hybrid transient, which contains more valuable information of traps than the single trapping or detrapping transient was detected and analyzed. Three traps with different time constants were determined and their...
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