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On behalf of the Conference Committee, we would like to welcome you to the 2016 International Conference on Solid-State and Integrated-Circuit Technology (ICSICT). The 13th in its series, ICSICT 2016 goes to the beautiful city - Hangzhou for four days from Oct. 25th to 28th, along with the 30th anniversary celebration of ICSICT.
This paper describes a complete process/design co-optimization methodology based on Fully Depleted SOI (FDSOI) technology. A process optimization is detailed through significant effective capacitance reduction, in order to optimize jointly frequency/leakage ratio and high frequency performances. In this objective, an efficient and low cost offset-spacers morphology has been designed to achieve maximum...
The power consumption in electronic devices is the major challenge as increasing the demand of IC chips. To lower the VDD and AC power (PAC), both high mobility material and steep turn-on device technology are useful. The ferroelectric high-κ HfZrO MOSFET can realize not only a small sub-threshold slope (SS) <60 mV/dec for low VDD and PAC, but also a smaller aspect ratio FinFET. The small bandgap...
High crystal quality ultrathin Ge and Ge0.96Sn0.04 channels are epitaxially grown on SOI and Si bulk, respectively, and high mobility pMOSFETs are fabricated. Low-temperature Si2H6 passivation of Ge and GeSn is utilized to form a high quality SiO2/Si interfacial layer between the high-κ dielectric and channels, leading to a substantial reduction of Dit. Ge and GeSn pMOSFETs achieve the improved μeff...
We propose a novel non-classical complementary metal oxide semiconductor (CMOS) inverter, which is composed of a Gated control NNP for driver N-type transistor (Gated-NNP) and a Gated control PPN for load P-type transistor (Gated-PPN). These two transistors have the same doping architecture with tunnel field effect transistor (TFET), but not use tunneling current mechanisms to achieve complementary...
Launched in 2006, Nanoelectronics Research Initiative (NRI) is jointly funded by the US semiconductor industry and government agencies to support university research to explore non-conventional low-energy technologies that can outperform CMOS on critical applications in ten years and beyond. Alternative state variables, novel mechanisms, and emerging materials have been investigated to achieve low-power...
In this paper, we explore the potentialities of TFET-based circuits operating in the ultra-low voltage regime. We show that the problem of unidirectional transport in 6T SRAMs can be solved by employing outward-facing access-transistors and suitable voltage levels during the read. We propose the level shifter as a key application domain of the hybrid TFET-MOSFET deployment strategy. By using the full...
In this work, we present our experimental results on Si GAA NW TFET inverters. The ambipolarity of both n- and p-TFETs was successfully suppressed by employing a drain spacer to create an intrinsic Si region between the drain and the gate, the so-called drain-gate underlap. The complementary TFET inverters show a steep transition between high/low states. Compared with the ambipolar TFET inverter,...
In this work, the SiGe nanowire pMOSFETs (NWT) for 7nm and beyond with Ge component varies from 20% to 90% are simulated by different methods including drift-diffusion (DD) vs Monte Carlo (MC) method for transport, and the Poisson-Schrödinger solver(PS) vs the density gradient (DG) approach for quantum effect. The impact of Ge component variation on the performance of pMOSFETs is also evaluated.
In this paper, a new steep-slope device concept of resistive-gate field-effect transistor (RG-FET), which is operated by electrically induced abrupt resistance change of gate stacks, is discussed in detail and experimentally optimized. The fabricated RG-FET demonstrates both an ultra-steep subthreshold slope of below 5mV/dec over almost 2 decades of drain current and a high on-current competitive...
In this article, we demonstrate plasma-enhanced atomic layer deposition (PEALD) as an effective passivation technique to establish high interfacial quality of high-k/InGaAs structures. Performing PEALD-AlN as an interfacial passivation layer (IPL), excellent capacitance-voltage (C-V) characteristics have been achieved for the HfO2/n, p-In0.53Ga0.47As MOSCAPs. The effects of AlN-IPL on the effective...
The voltage dependence of the low-frequency noise of GaN/AlGaN HEMTs is usually modeled in terms of mobility fluctuations. Noise measurements in commercial devices before and after proton irradiation and/or voltage stress have been found instead to be more consistent with number fluctuations. Low-frequency noise measurements vs. temperature show defect-related peaks in energy at ∼ 0.2 eV, ∼ 0.5 eV,...
Radio frequency (RF) energy harvesting circuit using a 20 nm InAs double-gate n-channel TFET has been studied. RF-DC converter using a two-stage cross-coupled rectifier is evaluated. Rectifier power conversion efficiency (PCE) at low input power using TFET shows noticeably better performance compared to its CMOS counterpart. Temperature sensitivity and threshold voltage variation effects on PCE are...
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