The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
In this article, we demonstrate plasma-enhanced atomic layer deposition (PEALD) as an effective passivation technique to establish high interfacial quality of high-k/InGaAs structures. Performing PEALD-AlN as an interfacial passivation layer (IPL), excellent capacitance-voltage (C-V) characteristics have been achieved for the HfO2/n, p-In0.53Ga0.47As MOSCAPs. The effects of AlN-IPL on the effective...
In order to mitigate the electric field crowdingingate dielectrics and solve the reliability issue, high dielectric constant (κ) materials such as Al2O3 was applied in SiC metal-oxide-semiconductor (MOS) capacitors. High quality thin film Al2O3 was deposited on 4H-SiC by thermal atomic layer deposition (ALD), followed by post deposition annealing (PDA). The PDA was conducted in oxygen atmosphere at...
Germanium (Ge) is not a new material but now spotlighted for beyond Si-scaled CMOS. Ge p-MOSFETs have been well investigated and its high performance has so far been demonstrated. On the contrary, an achievement of high electron mobility Ge n-MOSFETs is quite challenging due to a large amount of interface states near the conduction band edge. So, we first discuss how to overcome “intrinsic challenges...
Al2O3 films deposited as gate dielectrics on germanium (Ge) by atomic layer deposition (ALD) were post annealed in an ozone atmosphere at 450°C for 15, 25 and 35 minutes. The structure and chemical compound of Al2O3/Ge gate stacks were detected by X-ray photoelectron spectroscopy (XPS) measurements after ozone post annealing (OPA) treatments. It is confirmed by XPS measurements that this OPA treatment...
In this study, reactive-ion etching (RIE) of Ge in different ambient was systematically investigated. Several dominant parameters (applied power, gas flow rate and gas compositions) during the etching were considered to improve the profile of 3D Ge structures. Besides, it was experimentally confirmed that to obtain Ge sidewalls with small roughness and a large angle, adding O2 and an appropriate masking...
This paper presents a design of unique wireless remote controller, which utilizes WiFi wireless communication technology, providing a hand-held remote controller for an implantable stimulator. Based on MCU STC89C52RC, the controller is realized as a control terminal which issues instructions through WiFi module and receives the returned information, so that the controller realizes the control of the...
This paper describes an optimized dual RESERUF LDMOs with enhanced reliability for 30–50V automotive applications. The proposed LDMOS is designed to suppress drain current expansion due to Kirk effect. Simulation verified that the avalanche breakdown voltage is scalable from 32 to 60V, with the breakdown location always in the bulk, ensuring good ESD performance. Low specific on-resistance of 44.8mΩmm2...
This paper investigates a nondestructive method to measure the heat dissipation capability of slow-wave structure (SWS) of helix traveling-wave-tube (TWT). Bases on the transient temperature rise measurement technology, the thermal resistance model is established for accurate prediction of the heat dissipation of the SWS. And the thermal resistances in different positions of the SWS are acquired....
As the device size downscales, hot carrier aging (HCA) scales up and remerges as a major challenge to the reliability of modern CMOS technologies. The conventional method for predicting the HCA device lifetime is based on a power law kinetics and critically depends on the accuracy of the time power exponent, n. In this work, we study how to extract the n accurately. It will be shown that the widely...
With continuously growing integration density and decreasing feature size, chip reliability, especially oxide breakdown (OBD) reliability is a concerning topic for chip designers. In the past, architects have to assume either worst case workload or maximum supply level to assess chip OBD reliability, which is easily pessimistic and induces unnecessary back-tracking in the design flow. In this paper,...
In this paper, we report the positive bias temperature instability (PBTI) effects of the back-gated MoS2 n-MOSFET with Al2O3 gate dielectric. Multilayer MoS2 was used and all measurements are carried in vacuum to avoid the electric signal contamination by the top MoS2 surface water or oxygen molecules absorption. In the stress phase, the Id-Vg curve shifts to the positive gate bias direction. In the...
To date, gate stacks for high mobility semiconductors like Ge and InGaAs have been generally designed to minimise their interfacial trap density, and thus include an Al oxide layer diffusion barrier as a component. However, this is now known to lead to reduced reliability. The source of the problem is discussed and possible solutions based on an AlN or AlON layer component are suggested instead. First,...
This paper is an overview of low dielectric constant (low-k) materials developed for advanced interconnects and also presents recent innovative solutions for integration of ultra low-k dielectrics in ULSI devices. The innovative approaches include exploration of new candidate materials and technological solutions for interconnects integration in advanced technology nodes.
We proposed and fabricated amorphous indium-gallium-zinc-oxide thin-film transistors (IGZO TFTs) employing a novel organic-passivation layer (1-Methoxy-2-Propanol positive resist). The 1-Methoxy-2-Propanol passivated TFTs exhibit almost non-degraded electrical properties with carrier mobility, subthreshold swing of 5.9 cm2/Vs, 0.38 V/dec, respectively compared to the unpassivated TFTs. Besides, the...
Degradation of n-type low temperature poly-Si (LTPS) TFTs is investigated under bipolar gate pulses with a small drain bias. It is found that degradation behaviors are similar to those caused by the bipolar gate pulses with source and drain grounded. Dynamic hot carrier (HC) degradation is the dominant mechanism. However, device degradation also strongly depends on the drain bias. Four-terminal poly-Si...
We have developed a novel single-gate vertical channel (SGVC) 3D NAND Flash architecture. The device is a single-gate, flat-channel TFT charge-trapping device with ultra-thin body. The ultra-thin body TFT device enables tight initial Vt distribution as well as excellent short-channel effect that is comparable to and sometimes superior than the more prevailing gate-all-around (GAA) macaroni devices...
This paper presents a directly triggered asynchronous successive approximation register (SAR) logic with variable delay unit. With the help of the designed logic, the CDAC can be settled directly by the comparator result that avoids long propagation delay as conventional SAR logic does. Moreover, a variable delay unit is designed which provides more settling time to the last several bits to get more...
We have proposed two algorithms to demonstrate the relationship between W oxidation time and switching speed in this paper. The demonstration is carried out on a 128Kb test macro of AlOx/WOx bi-layer RRAM which was fabricated with 0.18µm standard logic process. Increasing the W oxidation time properly could achieve a faster switching speed while the overmuch oxidation time will result in performance...
Reliability of low-temperature poly-Si TFTs fabricated on flexible substrates is investigated under dynamic mechanical stresses such as bending and stretch. It is found that their degradation behaviors are similar, where threshold voltage shifts positively with no changes in the subthreshold behavior and channel mobility. The degradation is attributed to negative charge trapping induced by the mechanical...
A comparative investigation of the reliability of 60Coγ ray irradiation on bulk-Si substrate and SOI substrate double polysilicon self-aligned (DPSA) NPN bipolar transistors is presented. Bulk silicon based DPSA NPN transistors show severe current gain degradation at low injection level, and a monotonic increase in current gain degradation with decreasing Emitter-Base (E-B) voltage is observed. SOI...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.