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Self-organizing map (SOM) is an important statistical method for cluster analysis. The conventional single instruction multiple data (SIMD) solution sufficiently exploits the massive intrinsic parallelism of artificial neural networks. In this paper, we introduce a parallel-elementary-stream (PES) architecture for nearest-neighbor-search (NNS) based SOM model as an alternative to SIMD. The PES defines...
With the data growth related to the increase of devices with network access, the high speed Ethernet is widely used in various fields from big data center to high frequency transaction (HFT). However, the conventional software-based protocol stack consumes large amount of CPU time at full transmission rate, and leads to low performance such as high latency and low throughput. This paper presents a...
An off-chip calibration technology for the 6 Bit 30 Gsps time-interleaved ADC is presented in paper. The mismatches errors are calculated by calibration algorithm base on statistical approximation method. Negative feedback is used to reduce the three mismatches (skew, offset and gain mismatch). The off-chip calibration technology is implemented by FPGA. The measured results show that the average ENOB...
In order to split the bottleneck of stream cipher algorithms realized by general processors, flexible configurable and high-performance NBF instructions targeted at stream cipher processing are proposed. Analyzing the structures and operating characteristics of many stream cipher algorithms, the proposed NBF instructions can support different operation data widths, different write-back modes. Moreover,...
In this paper, a dual-field elliptic curve cryptographic processor is proposed to support arbitrary curves within 576-bit in dual field. Besides, two heterogeneous function units are coupled with the processor for the parallel operations in finite field based on the analysis of the characteristics of elliptic curve cryptographic algorithms. To simplify the hardware complexity, the clustering technology...
In this paper, a reliable and clear clock architecture and execution scheme is illustrated for the direct broadcast satellite set-top-box HD-SOC IC chip. To solve the stable and flexible clock/reset signals' generation and to satisfy the chip's debug/test bypass control, this paper gives a robust and flexible clock network realization. Also, the whole HD-SOC is manufactured with the TSMC90nm technology...
A physically-secure write scheme of Multi-time Programmable (MTP) RRAM for critical information storage is proposed and analyzed. The on-chip storage circuit can prevent physical attacks and illegal or malicious write operation. It improves the security level of existing MTP RRAM storage arrays by introducing an extra column storing protect-bits and using the address scrambling circuits. The proposed...
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