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This paper proposes the automatic design method of comparator circuit by combination of game tree search and partial optimization. Because game tree search can remove redundant calculation, simulation time can be reduced. Using partial optimization can confirm the convergence of the optimize function of HSPICE. Thus, the proposed automatic designed circuit can satisfy the required specific. Compared...
This paper presents device and mixed-mode simulations of single photon avalanche diode (SPAD) device. Device simulations show that the breakdown mechanism of our diode is indeed avalanche. Mixed-mode simulations can accurately simulate the ignition of the detector due to photon absorption, the fast avalanche current build-up, the self-sustaining charge-multiplication process, and the self-quenching...
This paper presents a novel hardening triple-well design for an six-transistors CMOS memory cell fabricated in 65 nm feature size. The new approach calculates the effects of single event transient (SET) with junction currents, which is derived based on device physics. Simulation presents that charge collection can be effectively mitigated with the use of guard ring contact in triple-well CMOS process...
Power supply fluctuation can be potential threat to the correct operations of microprocessors, in the form of voltage emergency that happens when supply voltage drops below a certain threshold. Noise sensors can be added to the chips to detect the voltage emergencies. But these deliberately inserted sensors brings extra design and calibration cost, and therefore, they are only added to a limited number...
A surface-potential-based compact model for the doped polysilicon (poly-Si) thin-film transistors (TFTs) is proposed in this paper. By develop in gap proximate explicit solutions of the surface potential from the Poisson's equation, we can express the drain current as explicit functions of applied voltages with using the charge sheet approach. Compared with the previous models, high accuracy and efficiency...
A closed-form drain current model for amorphous oxide semiconductor thin-film transistors is proposed in this paper. By adopting the effective charge density method and reformulating Lambert W function as two different exponential terms in different regions, both non-degenerate and degenerate conduction regimes are taken into account. Furthermore, an I–V model considering both the trapped and free...
This paper presents compact modeling for multi-domain system-level simulation based on multi-physics that considers the energy conservation condition, in terms of respective potential and flow quantities. Models for both electrical and non-electrical domains are developed to design a flexible blood pumping system where the blood flow is driven by electrically control organic actuators. The electrical...
In this work the Zero Temperature Coefficient (ZTC) is investigated experimentally using state-of-the-art industrial technologies like Ultra-Thin Body and Buried Oxide (UTBB) and triple-gate FinFETs (irradiated and/or strained devices), both fabricated on Silicon On Insulator (SOI) wafers. A simple analytical model to analyze the behavior of the gate-source voltage at the Zero Temperature Coefficient...
In this paper, a semi-analytical model for the gate-to-source/drain fringing capacitance (Cf) of MOSFET including process variations is presented. Cf is defined as a layout-dependent parasitic capacitance separated from gate-to-contact capacitance (Cco), and is composed of several dual-k perpendicular-plate capacitances. Layout-dependent coefficients such as gate to contact space (CPS) and contact...
A double-π equivalent circuit model well-fitted for on-chip inductors with GaN process is presented in this paper. The equivalent circuit is made up of two cells and can feature the frequency-dependent characteristics well in a wide range of frequency up to 20GHz. The parameter extraction is conducted based on the improved characteristic function method according to four parts. The validation includes...
TSV (Through-silicon Via) meets the demands of high speed and low power consumption in 3D integrated circuits. However it faces challenge in signal integrity problem such as crosstalk. TSV to TSV coupling is the most significant crosstalk problem in TSV based 3D ICs. This paper presents a quantitative estimation on the TSV to TSV crosstalk induced interconnect delay, trying to find the worst interconnect...
Neutron radiation induced soft error rate (SER) of semiconductor devices is still an important issue. Both SOI FinFET and bulk FinFET are simulated to analyze the sensitivity to neutron radiation, including particle transport simulation, device simulation and circuit simulation. The results demonstrate that bulk FinFET can deposit more energy due to larger sensitive volume. And the peak value of current...
In this paper, we present an easy to use 4-step design method for film bulk acoustic resonator (FBAR) filters, and demonstrated by a FDD-LTE band 7 FBAR Rx filter design case. According to the center frequency and bandwidth of FBAR filter, we determine thickness of each film in the FBAR film stack at the step 1. The step 2 gets the filter's circuit architecture. In the step 3, we obtain the active...
As the technology scales down, the single-event transient (SET) has become a great concern for the reliability of integrated circuits (ICs). A novel time redundant flip-flop structure is proposed to detect and correct the SET pulse. The most advantage of this structure is that it has very little setup and hold time overhead and the architecture need not be modified to recover the system. HSPICE simulation...
The shallow junction is used in the PDSOI technology. Unfortunately, the standard diode model maybe not suit to this PN junction. A simulation model is proposed based on the PDSOI process. The additional influence of the voltage bias of the junction to the capacitance is considered in this model and then the model is well verified by the measured data.
In this paper a SPICE model of bi-layer and bipolar metal oxide resistive random access memory (RRAM) is proposed. Stepped reset phenomenon in bipolar RRAM is included and the impact of buffer layer thickness on Ireset is reproduced. The model is verified by experimental results from AlOx/WOx based RRAM [1,2]. This model is useful for multi bits storage circuit design, read reference circuit design...
This paper presents a process, voltage, and temperature (PVT)-independent constant-gm bias circuit, designed in 0.18µm CMOS technology. In this paper, the conventional precise off-chip resistor is replaced by a MOSFET operating in triode region with a novel bias circuit, which behaves like a PVT-independent resistor. Simulations show that the maximum gm variation across process corners is ±5.2%, and...
A physically-secure write scheme of Multi-time Programmable (MTP) RRAM for critical information storage is proposed and analyzed. The on-chip storage circuit can prevent physical attacks and illegal or malicious write operation. It improves the security level of existing MTP RRAM storage arrays by introducing an extra column storing protect-bits and using the address scrambling circuits. The proposed...
A LNTA with robust improvement of IIP3 over temperature and process is proposed. Four auxiliary transistors are employed to achieve 3rd nonlinearity compensation using DS (derivative superposition) method. In order to maintain the high IIP3 over process and temperature (PT) variation, transistor's nonlinearity under PT is explored and corresponding bias circuit is built to keep enhancement in IIP3...
A comprehensive behavioral model of Track-and-Hold Amplifier (THA) based on GaAs HBT, implemented in MATLAB-SIMULINK platform, is presented in this paper. The main error sources of the holding capacitor and non-linear on-resistance are investigated, and the relative non-idealities are modeled. With the behavioral model, SIMULINK simulations were performed to analyze the non-ideal error sources and...
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