The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
The three-dimensional (3D) nature and continued dimensional scaling of Fin-, Nanowire-, and Gate-All-Around-FETs raise a host of unique challenges to device and process design that impact both performance and yield. We highlight selected technology challenges and solutions, specifically doping requirements for isolation, SD/E, and contact, as well as a new advanced planarization technique.
In this paper, a novel triple reduced surface field (RESURF) LDMOS with N-top layer based on substrate termination technology (STT) is proposed. The analytical models of surface potential, surface electric field, breakdown voltage (BV) and optimal integrated charge of N-top layer (Qntop) for the novel triple RESURF LDMOS are achieved. Furthermore, STT is applied to avoid the premature avalanche breakdown...
A novel trench IGBT with a high-k (HK) buried layer below the trench gate is proposed and investigated by simulation. The HK dielectric causes a self-adapted assistant depletion of the n enhancement layer. This not only increases the n enhancement layer doping concentration and thus lowers the on-state losses without compromising the switching performance or the breakdown rating. The forward voltage...
A surface-potential-based compact model for the doped polysilicon (poly-Si) thin-film transistors (TFTs) is proposed in this paper. By develop in gap proximate explicit solutions of the surface potential from the Poisson's equation, we can express the drain current as explicit functions of applied voltages with using the charge sheet approach. Compared with the previous models, high accuracy and efficiency...
This work investigates the static noise margin (SNM) of 6T SRAM composed of 2D semiconductor MOSFETs. A analytical current-voltage model for 2D semiconductor MOSFETs is applied to analyze all transistors in a 6T SRAM. Simulation model and method are built for basic 6T SRAM structure and that with S/D contact resistance. Effects on SNM of contact resistance and inefficient channel doping are studied,...
In this paper, we optimized a heterojunction SOI-TFET with high-k dielectric overlap on SiGe-source region. Mole fraction (x) of the Si(x)Ge(1−x) has an important influence in the performance of the TFET. The optimized device has achieved 50.9mV/decades SS, which breaks the 60mV/decades SS barrier. It has realized 107 Ion/Ioff ratios and the OFF-state leakage current can be lowed to 10−14 A/µm level...
An analytical model for threshold voltage of the normally-off GaN-based fin-shaped field-effect transistor (FinFET) is obtained. Analytical expressions for the threshold voltage and its roll-off effect are presented. Some design insights can be obtained from the results. The explicit expression for threshold voltage makes the model suitable to be embedded in circuit simulation and design tools.
An improved 4H-SiC MOSFET has been presented with fewer static and dynamic losses. The novelty of the structure lies in a combination of a heavily doped n-type epitaxial layer on the drift layer (Current Spreading Layer, CSL) and a p-type implantation introduced in the middle of the JFET area (Central Implant Region, CIR). Heavily-doped CSL could significantly reduce the specific on-resistance by...
A novel 4H-SiC metal semiconductor field effect transistor with localized high-doped P-buffer layer is proposed in this paper. Compared with conventional structure, because of the higher doped concentration in the P-buffer layer between the gate and the drain, greater depletion layer generates and extends to the channel, which reduces the concentration of channel carrier and modulates electric field...
A novel high-voltage trench SOI LDMOS with ultra-low specific on-resistance (Ron,sp) is proposed and it features a Trench-Field-Enhanced (TFE) structure around the deep trench dielectric layer. The TFE structure consists of an L-shaped p-region, a symmetrical-L-shaped n-region and two high-doping p+ regions. In the OFF state, as the trench-field-enhanced effect (TFE-E), electric field in the bulk...
GaN-based vertical field effect transistors (VFETs) are very promising in various power switching applications owing to their high current density and small chip size. However, it is still challenging to obtain high breakdown voltage (BV) and low on-resistance (Ron) in the practical VFETs. Design and simulation of the device structures are necessary in shortening the device development progress. In...
In this paper, we studied effects of doping concentration on the semi-floating gate (SFG) image sensor by Sentaurus technology computer aided design (TCAD) simulation. Our results show that the doping concentration of about 6e16 cm−3 for both n-well and p-well is appropriate for the SFG sensor. The doping concentration plays an important role on the output current range and the sensitivity of the...
By using the MOS energy band diagram and Negative Bias Temperature Instability (NBTI) degradation model, an equation of NBTI degradation with channel doping concentration has been derived. Meanwhile, a new NBTI inhibition method by using different doping concentration has been proposed. The quantitatively calculation and simulation results show that, with the proposed method, the NBTI inhibition rate...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.