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The Ultra High Definition (UHD) broadcasting is being prepared to start globally. However, due to a huge amount of data compared with HD data, a processing them in real-time is very difficult. The editing of broadcasting is more difficult because it has to support multiple channels simultaneously. In this paper, we propose a dedicated Very Large Scale Integration (VLSI) to accelerate and control the...
This paper presents hardware architecture with low-complexity face detection (FD) and parallel processing of local binary pattern (LBP) generation and adaptive boosting (AdaBoost) algorithm using Haar features for the intelligent service robot system. We designed a fully pipelined architecture implemented with the design techniques, such as variable image scaling and parallel processing multiple classifiers...
This paper presents novel hardware architecture with low-complexity color conversion scheme and parallel processing of red region detection for the applications of automatic traffic sign detection system. By the inherent parallelism of the various red region detections, we designed a fully pipelined architecture implemented on the FPGA platform. The proposed architecture enables a real-time traffic...
In this paper, we present a FPGA implementation of face detection hardware (HW) and also address face recognition software (SW) on virtual platform. We apply very deeply-cascaded classifier which is composed of heterogeneous feature-classifiers to capture various characteristics of images. We use 2 step classifiers, the first searches for the coarse features and the second for the fine features. Both...
An ECG monitoring system is implemented by using an android smart phone, an FPGA chip, a comparator, a resistor, a capacitor and an ECG front-end amplifier circuit. The FPGA chip includes a digital circuit block for delta modulator and a USB 1.1 PHY/LINK. The digital circuit block for delta modulator includes a sampler(D flip-flop), a sinc filter and a FIR filter. The delta modulator consists of the...
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