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This paper will examine challenges in future device scaling and the implications arising from difficulties in delivering scaling benefits from devices to the circuit level, and ultimately up to the system level. These implications will serve to highlight opportunities in design-technology interactions to aid in overall system scaling.
Nonvolatile power-gating (NVPG) that is a power-gating architecture employing nonvolatile retention is expected as a highly efficient energy reduction technique for high-performance microprocessors and mobile/wearable SoC devices. In this paper, the NVPG architecture for SRAM is demonstrated. A 1kb nonvolatile SRAM (NV-SRAM) array with the peripheral circuits is implemented using 65nm silicon-on-thin-buried-oxide...
We investigated the floating gate memory based on MoS2 channel with metal nanoparticle charge trapping layer and polymer tunneling dielectric. Here, highly conformal and stable polymer insulator layer deposited via initiated chemical vapor deposition (iCVD) facilitates the fabricated floating gate memory to endure a substantial electrical stress significantly. To form a selective density and controllable...
Nowadays there are two big obstacles for further progress in CMOS device technology. The energy dissipation due to leakage and the energy required to copy information between memory and processor. Even though cutting the power of unused circuits reduces the leakage dissipation to zero, it causes the loss of the locally stored information. Thus, it must be copied back from memory, when the circuit...
Ferroelectric random access memories (FRAM) are nonvolatile memories which allow a fast access time and a low power consumption. State-of-the-art devices are based on the perovskite lead zirconate titanate (PZT), which suffers from CMOS incompatibility resulting in scaling issues. The discovery of the ferroelectricity in doped hafnium oxide enabled scaled 3D memory devices. A variety of dopants has...
We assess the impact of the conductance response of Non-Volatile Memory (NVM) devices employed as the synaptic weight element for on-chip acceleration of the training of large-scale artificial neural networks (ANN). We briefly review our previous work towards achieving competitive performance (classification accuracies) for such ANN with both Phase-Change Memory (PCM) [1], [2] and non-filamentary...
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