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A new process variation monitoring circuit (PVMC) has been proposed in the paper. The goal is to generate a digital signal/code which (code value) will characterize the process corner. The circuit uses only metal-oxide-semiconductor (MOS) transistors to detect variation of their parameters, or process corner by generating digital signals. Process variation is detected based on variation of parameters...
In this paper, we analyze the impact of voltage, temperature and body-biasing on the detection of resistive short defects for low-VT (LVT) and regular-VT (RVT) configurations of a 28nm UTBB FDSOI (Ultra Thin Body & BOX Fully Depleted Silicon-On-Insulator) technology. We implemented a similar design in each configuration and compared their electrical behaviors with the same resistive short...
In this paper, a low power 5-bit hybrid flasharchitecture is proposed. The proposed analog-to-digital con-verter (ADC) uses appropriate combination of both conventionaldouble-tail comparators and standard cell comparators. Stan-dard cell comparators are used to reduce power consumption. Thus, the proposed hybrid architecture results in extendeddynamic range when compared to standard cell and thresholdinverter...
With current tools and technology, someone who has physical access to a chip can extract the detailed layout of the integrated circuit (IC). By using advanced visual imaging techniques, reverse engineering can reveal details that are meant to be kept secret, such as a secure protocol or novel implementation that offers a competitive advantage. A promising solution to defend against reverse engineering...
Body biasing (BB) in bulk CMOS is an important tool for circuit designers that enables dynamic modulation of device thresholds post-fabrication, thus potentially improving yields, or allowing the circuit to adapt to different power modes, such as fully active or sleep. Fully-depleted silicon-on-insulator (FDSOI) FETs, such as ultrathin body (UTB) devices, may benefit from the same effect when the...
Continuous technology scaling and increased demand for computational power have introduced a paradigm shift in manycore design requirements. On the other hand, tight power budgets and limitations of voltage scaling are throttling the ability to optimally exploit the potential of these systems, leading researchers to adopt aggressive voltage scaling techniques such as Near-Threshold Computing (NTC)...
An accurate, robust CMOS voltage reference biasedin subthreshold region with integrated temperature sensor circuit has been proposed in 180nm technology node using UMC RF process for IoT and low cost SoC applications. In UMC 180nm node the proposed reference voltage has an accuracy of 65 ppm/°C over 3σ variation in process and ±10% variation in supply, in the...
This paper presents a method to use floating gate (flash) transistors to implement low power ternary-valued digital circuits targeting handheld and IoT devices. Since the threshold voltage of flash devices can be modified at a fine granularity during programming, our approach has several advantages. For one, speed binning at the factory can be controlled with precision. Secondly, an IC can be re-programmed...
Nowadays, typical (memory) designers add design margins to compensate for uncertainties, however, this may be overestimated leading to yield loss, or underestimated leadingto reduced reliability designs. Accurate quantification of alluncertainties is therefore critical to provide high quality andoptimal designs. These uncertainties are caused by zero-timevariability (due to process variability), and...
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