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Parallel and monolithic 3D-integration directions offer pathways to realize 3D integrated circuits but still lead to layer-by-layer implementations. This mindset causes challenging connectivity and alignment between layers when connected in 3D, with a routing access that can be even worse than 2D-CMOS, which fundamentally limits their potential. To fully exploit the opportunities in the third dimension,...
To alleviate interconnect scaling problem, Network-on-Chip (NoC) has evolved as a standard to design advanced Multiprocessor System-on-Chip (MPSoC). Furthermore, three-dimensional (3D) integration has been proposed recently as an alternative to meet interconnection scaling demands. To design three-dimensional NoC (3D NoC) based systems, the communication channel across vertical direction of an extended...
Increased power density and high temperatures are looming issues in many-core processors. Technology scaling trends, cooling limitations, and stringent application requirements make these issues rather difficult to handle. Consequently, it is imperative to design solutions that are effective and also scale well with increasing core counts. In this work, we present an application mapping framework...
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