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Presently, almost all timing analyses and optimization tools are based on the strategy of setup and hold time constrained flip-flop timing model. However, this is a big mismatch with the timing characteristic of the real life flip-flops, which is so called flexible flip-flop timing, in which the clock-to-Q delay of every flip-flop may vary dynamically according to its setup and hold skews. This work...
To support emerging applications in autonomous and semi-autonomous driving, next-generation automotive systems will be equipped with an increasing number of heterogeneous components (sensors, actuators and computation units connected through various buses), and have to process a high volume of data to percept the environment accurately and efficiently. Challenges for such systems include system integration,...
Subthreshold ultra-low-power passive RFID tag's baseband processor core design with custom logic cells is presented in this paper, based on EPC C1G2 protocol. To deal with the critical timing and wide-range-PVT variation problems of the processor at very low power supply, and for the consideration of limited availability of RF power, power-aware scheme is applied to the key modules, including PIE...
Meeting timing requirements and improving routability are becoming more challenging in modern design technologies. Most timing-driven placement approaches ignore routability concerns which may lead to a gap in routing quality between the actual routing and what is expected. In this paper, we propose a routing-aware incremental timing-driven placementtechnique to reduce early and late negative slacks...
Error detection and correction based on double-sampling is used as common technique to handle timing errors while scaling Vdd for energy efficiency. An additional sampling element is inserted in the critical paths of the design, to double sample the outputs of those logic paths at different time instances that may fail while scaling the supply voltage or the clock frequency of the design. However,...
In this paper, we propose a cycle-accurate monitor that can efficiently detect timing violation based fault attacks. The proposed monitor detects clock or voltage manipulations by monitoring the external clock using an internal Ring Oscillator. The monitor is low cost in terms of area and power consumption and can be easily implemented using the standard cell based VLSI design flow. In addition to...
The wide use of Multi-processing systems-on-chip (MPSoCs) in embedded systems and the trend to increase the integration between devices have turned these systems vulnerable to attacks. Malicious software executed on compromised IP may become a serious security problem. By snooping the traffic exchanged through the Network-on-chip (NoC), it is possible to infer sensitive information such as secrets...
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