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Mission critical applications face a security risk when they use third-party ICs for their speed and/or technology benefits. SecCheck is an architectural framework that securely incorporates fast, untrusted third-party cores (3PCs). It takes a comprehensive approach, providing for all of the different traditional fault tolerance techniques, to verify the 3PCs' functioning. The verification is done...
This paper presents a silicon-proven fault tolerant FPGA architecture that can repair a wide range of hardware faults. This new architecture does not require fine-grained location of fault, and the error map is stored in non-volatile memory that is monolithically integrated on top of the CMOS circuit. Redundancy operations are fully self-contained and do not affect data streaming in and out of the...
Achieving high reliability against transient faults poses significant challenges due to the trends of technology and voltage scaling. Thus, numerous soft error mitigation techniques have been proposed for masking Soft Error Rate (SER) in logic circuits. However, most soft error suppression approaches have significant overheads in terms of area, power consumption, and speed performance degradation...
As the device size decreases, the reliability degradation caused by soft-errors and multiple component error due to a single soft-error are becoming serious problems in VLSIs. In this study, we propose a method to synthesize single soft-error tolerant datapaths based on soft-error detection by duplication and comparison and correction by retry. Under the assumption that a single soft-error does not...
Most prior work on hardware reliability make use of module (spatial) redundancy or time redundancy. In the first case, these methods assume that each module is exactly the same. Multiple module replicas implementing the same logic function are executed in different hardware channels and a voting scheme detects if the outputs match or not. In the second case, they re-compute the result using the same...
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