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Partial reconfiguration (PR) enhances traditional FPGA-based reconfigurable embedded systems with benefits such as reduced resource requirements and increased functionality. Since fully realizing these PR benefits requires extensive PR design flow knowledge, as well as the target FPGA's low-level architectural details, PR has not yet gained widespread usage. To alleviate manual design-time effort,...
Meeting timing requirements and improving routability are becoming more challenging in modern design technologies. Most timing-driven placement approaches ignore routability concerns which may lead to a gap in routing quality between the actual routing and what is expected. In this paper, we propose a routing-aware incremental timing-driven placementtechnique to reduce early and late negative slacks...
This paper represents a framework for on-chip delay measurement, which will be helpful in measuring the impact of device level variability on memory access time. Commercial frameworks for simulating circuit degradation due to device aging effects are not available. 1 KB SRAM is used as test setup for which on-chip read access time measurement is performed. On-chip delay measurement is performed using...
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