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Convolutional Neural Network (CNN) has become a successful algorithm in the region of artificial intelligence and a strong candidate for many applications. However, for embedded platforms, CNN-based solutions are still too complex to be applied if only CPU is utilized for computation. Various dedicated hardware designs on FPGA and ASIC have been carried out to accelerate CNN, while few of them explore...
To support emerging applications in autonomous and semi-autonomous driving, next-generation automotive systems will be equipped with an increasing number of heterogeneous components (sensors, actuators and computation units connected through various buses), and have to process a high volume of data to percept the environment accurately and efficiently. Challenges for such systems include system integration,...
Cyclostationary feature detection for spectrum sensing incognitive radio network has significant prospect in future wirelesscommunicationsystems. This work deals with the very-large scaleintegration(VLSI) architectural transformation of such detection algorithmfor field-programmable gate-array (FPGA) prototyping andapplication-specific integrated-circuit (ASIC) design. System level designof this detection...
Dynamic Adaptive Neural Network Arrays (DANNAs) are neuromorphic systems that exhibit spiking behaviors and can be designed using evolutionary optimization. Array elements are rapidly reconfigurable and can function as either neurons, synapses or fan-out elements with programmable interconnections and parameters. Currently, DANNAs are implemented using Field Programmable Gate Arrays (FPGAs) and are...
A variety of hardware security primitives have been developed in recent years, aimed at mitigating issues such as integrated circuit (IC) piracy, counterfeiting, and side-channel analysis. For example, a popular security primitive for mitigating such hardware security vulnerabilities is the physical unclonable function (PUF) which provides hardware specific unique identification based on intrinsic...
Convolutional Neural Networks (CNNs) have revolutionized the world of image classification over the last few years, pushing the computer vision close beyond human accuracy. The required computational effort of CNNs today requires power-hungry parallel processors and GP-GPUs. Recent efforts in designing CNN Application-Specific Integrated Circuits (ASICs) and accelerators for System-On-Chip (SoC) integration...
Energy consumption has become a major concern in portable applications. This paper proposes an energy-efficient design of the Secure Better Portable Graphics Compression (SBPG) Architecture. The architecture proposed in this paper is suitable for imaging in the Internet of Things (IoT) as the main concentration is on the energy efficiency. The novel contributions of this paper are divided into two...
This paper represents a framework for on-chip delay measurement, which will be helpful in measuring the impact of device level variability on memory access time. Commercial frameworks for simulating circuit degradation due to device aging effects are not available. 1 KB SRAM is used as test setup for which on-chip read access time measurement is performed. On-chip delay measurement is performed using...
In this paper, a low power 5-bit hybrid flasharchitecture is proposed. The proposed analog-to-digital con-verter (ADC) uses appropriate combination of both conventionaldouble-tail comparators and standard cell comparators. Stan-dard cell comparators are used to reduce power consumption. Thus, the proposed hybrid architecture results in extendeddynamic range when compared to standard cell and thresholdinverter...
Mission critical applications face a security risk when they use third-party ICs for their speed and/or technology benefits. SecCheck is an architectural framework that securely incorporates fast, untrusted third-party cores (3PCs). It takes a comprehensive approach, providing for all of the different traditional fault tolerance techniques, to verify the 3PCs' functioning. The verification is done...
Binary Exchange Algorithm (BEA) always introduces excessive shuffle operations when mapping FFTs on vector SIMD DSPs. This can greatly restrict the overall performance. We propose a novel mod (2P-1) shuffle function and Mod-BEA algorithm (MBEA), which can halve the shuffle operation count and unify the shuffle mode. Such unified shuffle mode inspires us to propose a set of novel mod (2P-1) shuffle...
With many advantageous features such as softness and better biocompatibility, flexible electronic device is a promising technology that can enable many emerging applications. However, most of the existing applications with flexible devices are sensors and drivers, while there is nearly no utilization aiming at complex computation, because the flexible devices have lower electron mobility, simple structure,...
Energy consumption has long been one of the main constraints that has guided the design of embedded processors. VLIW architectures are well-suited for this field, since they have a simpler microarchitecture and reduced energy consumption due to their static ILP exploitation. As we will show in this paper, intelligent use of the compiler allows for power gating at a finer grain (i.e., functional units,...
Shift-add/subtract circuits constitute the basic building blocks of several frequently used complex arithmetic units such as multiple constant multipliers, exponentiation circuits, fast division circuits, CORDIC rotators, logarithmic and residue number conversation units, etc. Fine-grained pipelined designs of these arithmetic units have strong potential to improve the power-performance-reliability...
Coarse-Grained Reconfigurable Architectures (CGRAs) are promising high-performance and power-efficient platforms. However, their uses are still limited because of the current capability of the mapping tools. This paper presents a new scalable efficient design flow to map applications written in high level language on CGRAs. This approach leverages on simultaneous scheduling and binding steps respectively...
Complex Event Processing refers to different mechanisms such as event correlation and event patterns detection for processing multiple events with the goal of inferring the complicated ones. While a simple event may provide trivial information, combining several of them can help in deriving more useful information. Detecting the complex events requires huge processing capability. The existing hardware...
Convolutional neural network (CNN), well-knownto be computationally intensive, is a fundamental algorithmicbuilding block in many computer vision and artificial intelligenceapplications that follow the deep learning principle. This workpresents a novel stochastic-based and scalable hardware architectureand circuit design that computes a convolutional neuralnetwork with FPGA. The key idea is to implement...
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