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We demonstrate single- and double-gated (SG & DG) field effect transistors (FETs) with a record source-drain length (LS/D) of 15 nm built on monolayer (tch∼0.7 nm) and 4-layer (tch∼3 nm) MoS2 channels using monolayer graphene as the Source/Drain contacts. The best devices, corresponding to DG 4-layer MoS2-FETs with LS/D=15 nm, had an Ion/Ioff in excess of 106 and a minimum subthreshold swing (SS...
We introduce for the first time a novel integration scheme of CBRAM cells, where the Cu electrode is patterned using a subtractive dry-etching process. We demonstrate excellent performances of 30nm-size cells (1µs-write at ≤50µA, >106 endurance, excellent retention at 150°C) as well as scaling potential of CBRAM down to 10nm-node using 5nm-thick Cu electrodes.
We present a state-of-the-art fabrication technology and physics-based model for molybdenum disulfide (MoS2) field effect transistors (FETs) to realize large-scale circuits. Uniform and large area chemical vapor deposition (CVD) growth of monolayer MoS2 was achieved by using perylene-3,4,9, 10-tetracarboxylic acid tetrapotassium salt (PTAS) seeding. Then, a gate first process results in enhancement...
We report on the first demonstration of ultra-thin body (50 nm), low defectivity 200 mm InGaAs-on-insulator (-OI) fabricated by direct wafer bonding technique (DWB) as well as a replacement gate process for self-aligned fully depleted InGaAs MOSFETs. These combined achievements highlight the viability of our approach for the VLSI integration of InGaAs at advanced nodes. Short channel replacement gate...
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