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An energy-efficient second-order ΔΣ modulator for low-power, low-frequency applications has been demonstrated. It uses a dynamic common-source integrator, where a MOSFET turns off after charge redistribution is completed. Thus, there are virtually no static current flows in the present integrator, reducing the power consumed by the ΔΣ modulator. A chip was fabricated as a proof of concept. A peak...
A direct-conversion RF-receiver IC implemented in 65nm CMOS, which has an RF front-end and all-digital differential time-based analog-to-digital converter (TAD) with 4-time-interleave technique for high resolution, is presented. The RF front-end contains passive mixers using wideband gm-cells and switches. When OFDM 16QAM RF signal (input power: −45.4dBm, BW: 20MHz) of 500M, 1.5G, and 2.5GHz is demodulated,...
In this paper, an automatic gain control amplifier (AGC) is proposed. The proposed AGC aims at a large input and output swing with a rapid tracking capacity. Moreover, the proposed AGC has a quite simple structure, which is very important for High intensity focused ultrasound (HIFU) applications in which an array of identical circuits must be used. The designed circuit was simulated in a CMOS 0.35μm...
The complexity of a radiofrequency (RF) circuit design comes from the large number of parameters to be adjusted. The constant node shrink in CMOS process and variation of technology skills significantly contribute to this complexity. The paper reports on a reliable and portable design methodology based on the inversion coefficient and applies it to the design of a Low Noise Amplifier (LNA). Both meeting...
Phase-Change Memory (PCM) is the most mature among back-end emerging memory technologies and a likely candidate for the next generation of non-volatile memories. This paper presents an innovative programming technique for the Low-Resistance State (LRS) in PCM. The technique consists of an appropriately shaped electrical pulse, capable of controlling the power provided to the memory cell in order to...
This paper presents in vivo measurements obtained from an implantable 64-channel neural recording Application Specific Integrated Circuit (ASIC) developed at IMSE and gives details of the computer interface used for real-time data acquisition. This interface connects the ASIC to a conventional 2.0 USB port by means of a Field Programmable Gate Array (FPGA). Communications are bidirectional and employ...
The estimation of mismatch-induced errors between the channels of a Time-Interleaved ADC is crucial for implementing an efficient calibration method. This step is often done with the assumption that all the noise sources have a white gaussian distribution. In this paper we analyze the statistical properties of noise components in wideband ADCs in terms of Probability Density Function (PDF) and Power...
Multi-phase oscillator is an essential block in digital communication systems especially phase shift keying PSK based systems. In this paper, a procedure for designing a multi-phase oscillator with any required phase shift is proposed, unlike the previous oscillator which generates equal phase shifts. This oscillator circuit is built using fractional-order elements to generate any distribution of...
Excessive test power dissipation results in over-testing, IR-drop, yield loss and even heat damage to the circuit under test (CUT). An efficient scan-shift power reduction scheme based on scan chain partitioning and test vector reordering is presented in this paper. After partitioning the scan chains into several segments equally, a heuristic ant colony optimization (ACO) algorithm is introduced to...
Nano metal-semiconductor contacts in sub-20 nm range have showed unusual electrical characteristics compared to conventional diodes. New devices based on nano Schottky junction have been proposed to overcome the limitations of CMOS devices. Here we introduce a new theoretical approach for studying the enhancement of the electric field at the interface, and then the net current along the junction....
3D-MPSoCs integrate cores of several vendors and support different applications on a single die, providing large performance and cost reduction. 3D-technology presents many security challenges and offers new opportunities to implement protection countermeasures. 3D-NoCs can be explored to assist the overall security of the system. In this work, we propose a 3D-NoC hardware architecture able to protect...
This paper presents a study of fractional order oscillators based on current feedback operational amplifiers (CFOA). Two general cases have been discussed for the oscillation frequency and condition with the use of two fractional order elements of different orders. Design procedure for the two general cases is illustrated with numerical discussions. Circuit simulations for some special cases are presented...
In this paper a comprehensive analytical analysis is performed based on a new accurate electrical model of silicon photomultiplier (SiPM) detectors. The proposed circuit model allows to accurately reproduce the SiPM output time response regardless of the particular technology adopted for the fabrication process, and can also be profitably exploited to perform reliable circuit-level simulations. A...
State-space modeling and analysis of a class of switched capacitor RF power amplifiers are introduced resulting in fast and accurate calculation of the output and supply-drawn power as well as of the voltage and current waveforms. Power derivation parameterized on component values and intermediate transformed impedances offers a tool for optimizing the switched capacitor RF power amplifier for maximum...
A 28nm FDSOI CMOS low power VCO working at 40 GHz frequency is presented in this paper. The VCO core only consumes 6mW from a 1 V supply voltage. A wide tuning range of 18.5 % from 38.3 GHz to 46.1 GHz is reached with a tuning voltage from 0 to 1 V A phase noise higher than −120.5 dBc/Hz at 10 MHz offset has been observed after post-layout simulations. A variable inductance approach has been chosen...
Co-designed Low Noise Amplifier (LNA) and dipole antenna in a RadioFrequency (RF) dedicated silicon technology, BÌCMOS9MW, are presented in this paper. The LNA is a two-stages cascode based on a SiGE:C 130 nm HBT optimized for maximum gain. The antenna is a dipole designed to match the LNA input impedance and maximize radiation diagram. Both are co-integrated directly on the silicon chip. The circuit...
This paper presents an auto tuning system using a variable synchronous switched capacitor for controlling the resonant frequency of a half bridge voltage mode resonant converter. This original tuning topology does not need the addition of any bulky magnetic and consequently is naturally compatible with MRI (Magnetic Resonance Imaging) equipments.
In this paper a new digital dedicated hardware IP module for extracting singular points from fingerprints is presented (in particular convex cores). This module comprises four main blocks that implement an image directional extraction, a smoothing process, singular point detection and finally, a post processing to obtain the exact location of the singular point. A Verilog HDL description has been...
This paper presents a simulation-based method for evaluating the static offset in discrete-time comparators. The proposed procedure is based on a closed-loop algorithm which forces the input signal of the comparator to quickly converge to its effective threshold. From this value, the final offset is computed by subtracting the ideal reference. The proposal was validated using realistic behavioral...
Secure implementations have two primary goals: being optimized (with respect to area, latency, power, or throughput) and secure against physical attacks, such as side channel analysis. Composite fields have been often proposed as a solution for the former problem, allowing implementations of the Advanced Encryption Standard targeted at resource constrained applications: additionally, they may also...
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