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CMOS utilizing high mobility Ge/III–V channels on Si substrates is expected to be one of promising devices for high performance and low power logic LSIs in the future [1, 2]. There can be several CMOS structures using III–V/Ge channels, as schematically shown in Fig. 1. Viable CMOS structures using III–V and/or Ge channels are still strongly dependent on coming progress in the device/process/integration...
Conference proceedings front matter may contain various advertisements, welcome messages, committee or program information, and other miscellaneous conference information. This may in some cases also include the cover art, table of contents, copyright statements, title-page or half title-pages, blank pages, venue maps or other general information relating to the conference that was part of the original...
Ge nanowire MOSFETs with a uniaxial compressive strain as high as 3.9% were demonstrated by 2-step Ge-condensation technique. Record high hole mobility (μeff = 1922 cm[su2}/Vs) and record-low off-current (2.7×10−9A/µm at Vd = −0.5 V) were achieved among scaled (sub-100nm Lg) Ge MOSFET for the device with the Lg of 45nm. These results indicate that strained-Ge channels have a potential to serve as...
The amount of internet traffic increases year by year. The bandwidth demands of internet consumers is ever increasing, although the costs at which improved services are offered does not scale at the same rate. The power consumption of components in the internet network is alarming and is an issue that urgently needs addressing as the technology which serves the internet is developed. Network providers...
Recent demonstrations of light emission from group IV materials such as Ge and its alloy with Sn renew the vision for the realization of an all group IV based opto-electronic platform. We compare some of these approaches to our strain method and mention rewarding research to further improve materials and concepts.
S/D epitaxial layers and SRBs are the most effective stressors in scaled FinFETs. While S/D stressors are well established, for SRBs the remaining technical difficulties are significant. However, its expected performance boost and enhanced scalability makes developing SRBs worthwhile, especially when combined with alternative channel materials.
In summary, we report an extremely high 2DHG mobility of 4500 cm2V−1s−1 and 777000 cm2V−1s−1 at 293 and 0.333 K, respectively, in a compressively strained Ge QW grown by industrial type RP-CVD on a standard Si(001) substrate. The obtained 2DHG mobility is substantially higher than those reported so far and in structures grown by research type epitaxial growth techniques, i.e. SS-MBE and LEPE-CVD....
Highly tensile strained Ge(Sn) layers epitaxially grown on GeSn strain relaxed buffer layer have been presented. Electrical characterization exhibits good interfacial quality of the high-k gate stacks employing HfO2 on Ge and strained Ge. These results mark a first step towards electronic device integration of low bandgap highly tensely strained group IV semiconductors.
With the Si-Ge-C SLs described in this paper, the bandgap nature (indirect/direct) and magnitude, as well as the band offsets relative to Si, can be varied significantly across the entire infra-red spectrum, depending on the SL composition and periodicity, and also on surface orientation. Devices that until now have required compound semiconductors are now possible to implement with Si-Ge-C SLs, which...
Poor electron mobility in n-channel Ge FETs is not intrinsic. We can engineer the Ge interface through understanding of thermodynamics in gate stack formation and of kinetics of both surface planarization and oxidation. Thus, Ge FETs are quite promising not only in p-channel but also in n-channel FETs.
A one-growth step fabrication scheme for strained Ge FinFET structures has been successfully developed and implemented in a device fabrication scheme. From device point of view, the concept including two growth steps might be even more favorable. However, it requires an improvement of the pre-epi oxide removal from Si1−xGex surfaces.
XRD techniques determined that 270 nm GaP grown on 400 nm Si0.85Ge0.15/Si(001) substrates by MOCVD is single crystalline and pseudomorphic, but carry a 0.07% tensile strain after cooling down to room temperature due to the bigger thermal expansion coefficient of GaP with respect to Si (Fig. 2). TEM and AFM examinations indicated a closed but defective GaP layer (Fig. 3(a)) with low root mean square...
We describe the use of LPCVD grown Ge layers on off-axis silicon wafers (200mm) as suitable templates for growth of subsequent III/V layers using solid source molecular beam epitaxy (MBE). A reproducible process for direct III–V semiconductor growth on Ge-coated Si substrates [1,2] has been developed using both single-wafer R&D MBE systems (Veeco GEN-III model) and multi-wafer production tools...
As Si-CMOS scaling has become increasingly challenging, III–V compound semiconductors such as InxGa1−xAs (x≥0.53) (InGaAs) are receiving much interest as channel material for nFET [1,2]. Together with SiGe as a pFET channel, they are considered as potential candidates to replace silicon for low power, high performance CMOS thanks to their better transport properties. A prerequisite in view of integration...
We have demonstrated that phosphorus delta-doping of germanium in ultra-high vacuum is a promising technique to tune doping at high densities (>1020 cm−3) in thin Ge films. Eventually, high doping densities on demand for photonic or electronic applications may be delivered by suitably choosing the total number of layers, tuning their separation in the ε-layer stack, and engineering the amount of...
In conclusion, a unique method to achieve high quality shallow n+/p junction by out-diffusion of phosphorus from poly-Ge has been demonstrated. The technology and key issues of poly-Ge deposition by LPCVD is presented. Results shown from diode I–V characteristics indicate feasibility of poly-Ge used for junction and contact realization.
This work compares the impact of implantation temperature ranging from cryogenic (−100 °C) to hot (400°C) on the performance of n+/p Ge junctions. Cryogenic implantation on bulk, planar Ge followed by a 400°C rapid thermal anneal leads to higher activation. lower junction depth, lower sheet resistance and lower junction leakage compared to RT and hot (400°C) implantation. The improved junction performance...
As dose as function of AsH3 exposure temperature is shown in Fig. 1. Temperature change after Si buffer deposition and AsH3 exposure are done in H2 or N2. For both cases the As incorporation is suppressed below 400°C. The incorporation behaviour is different from PH3 [3]. A possible explanation could be that limited hydrogen desorption from AsH3 molecule gas at lower temperature causes prevention...
n+-Ge layers with a dopant concentration of 1 × 1020 cm−3 and its dopant activation rate as high as 0.7 were obtained by optimizing the growth conditions in LP-CVD. Ti/n+-Ge contacts utilizing Ge:P layers with a carrier concentration of 7 × 1019 cm−3 exhibit ohmic property in contrast to the P ion-implanted Ge samples with almost the same P concentration and carrier concentration of 2 × 1019 cm−3...
With increasing complexity of processes and variety of materials used for semiconductor devices, stringent control of the electronic properties is becoming ever more relevant. Collinear micro four-point probe (M4PP) [1] based measurement systems have become high-end metrology methods for characterization and monitoring of sheet resistance [2,3] as well as sheet carrier density and mobility via the...
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