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This talk will give a general overview of the IBM Silicon Photonics program and specifically discuss CMOS compatible traveling wave electro-optic modulator design. A Non-Return-to-Zero Transmitter-link penalty calculation protocol for Mach-Zehnder Interferometric modulators based on the phase shifter efficiency-loss figure-of-merit will be presented. Our Transmitter-link penalty analysis protocol...
As we integrate hundreds of cores in the future, energy-efficiency and scalability of Network-on-Chips (NoCs) has become a critical challenge. In order to achieve higher performance-per-Watt than traditional metallic interconnects, researchers are exploring alternate energy-effident emerging technology solutions. In this paper, we propose to combine two emerging technologies, namely 3D stacking and...
Graphics processing units (GPUs) are increasingly critical for general-purpose parallel processing performance. GPU hardware is composed of many streaming multiprocessors, allowing GPUs to execute tens of thousands of threads in parallel. However, due to the SIMD (single-instruction multiple-data) execution style, resource utilization and thus overall performance can be significantly affected if computation...
On-chip wireless interconnects are being investigated for applicability on network-on-chip systems of contemporary Multiprocessor Systems-on-chip (MPSoCs). Targeting both 2D and 3D semiconductor technologies, wireless interconnects are established with multiple antennas on the same die or couplers on the layers of a 3D IC package. The wireless interconnects are typically considered as a hierarchical...
Modeling layout-dependent interconnect processing steps is useful to predict integrated circuit design behavior. We illustrate key data and steps in developing etch, electrochemical deposition (ECD), and chemical-mechanical polishing (CMP) models in order to predict chip topography. We utilize an interferometer for validation of models for the first time. Such models are useful to select optimal fill...
To meet energy-efficient performance demands, the computing industry has moved to parallel computer architectures, such as chip — multi-processors (CMPs), internally interconnected via networks — on-chip (NoC) to meet growing communication needs. Achieving scaling performance as core counts increase to the hundreds in future CMPs, however, will require high performance, yet energy-efficient interconnects...
As technology scales, wire delay due to interconnect resistance (R) and capacitance (C) is increasing. Thus, improvement of middle-of-line and back-end-of-line (BEOL) materials and process technology (e.g., to achieve reduced barrier material thickness or dielectric permittivity) has always been a key goal in the technology roadmap. However, to date there has not been any systematic quantification...
Clock tree synthesis (CTS) is a key aspect of on-chip interconnect, and major consumer of IC power and physical design resources. In modern sub-28nm tools and flows, it has become exceptionally difficult to satisfy skew, insertion delay and transition time constraints within power and area budgets, in part because commercial tools (with their many knobs) have become highly complex. This complexity,...
Incremental static timing analysis (iSTA) is the backbone of iterative sizing and Vt-swapping heuristics for post-layout timing recovery and leakage power reduction. Performing such analysis through available interfaces of a signoff STA tool brings efficiency and functionality limitations. Thus, an internal iSTA tool must be built that matches the signoff STA tool. A key challenge is the matching...
Increasing scope and applications of integrated optics necessitates the development of automated techniques for physical design of optical systems. This paper presents an automated, planar channel routing technique for integrated optical waveguides. Integrated optics is a planar technology and lacks the inherent signal restoration capabilities of static-CMOS. Therefore, signal loss minimizationas...
We propose a novel method to predict the worst-case noise using power distribution network impedance profile. Traditional target impedance method lacks of accuracy to estimate the worst-case noise. The convolution of impulse responses method can provide accurate noise prediction but cannot provide intuitive guidelines for the optimization. In this paper, we first analyze the ratio of the time-domain...
This paper quantifies the challenges, limits, and opportunities of interconnects for evolutionary and revolutionary semiconductor technologies of the future. Various exploratory devices and the delays associated with their transport mechanisms are quantified. Graphene is selected as the interconnect material of choice because of its excellent transport properties over the conventional Cu/low-K: interconnects...
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