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In this paper an approach to analysis of responsivity of MOSFET-based detectors of THz radiation has been presented. The author has analyzed the substrate modes that affect performance of antennas that are always used as a part of detecting structures, and should be accounted for by proper choice of the substrate geometry. Then, a methodology to combine extracted properties of an arbitrary antenna...
The Integrated Radiation Spectrometer is an electronic and optical solution for measuring the light spectra for wavelengths about 1050 nm with the sustained readout rate of 1 MHz. The device is built for determining the longitudinal charge distribution profile in an electron bunch.
In the paper we consider architecture of an analog dual delay locked loop (DLL). It uses an simply-implementable coarse delay line to push the loop close to lock state, and a fine programmable delay line to make small adjustments to the output phase. Both coarse- as well as fine-delay line are implemented as a cascades of variable-delay elements based on single-ended Schmitt triggers. For the correction...
This paper describes design of readout circuit destined for NMOS terahertz detectors. The proposed architecture bases on chopper amplifier and instrumentation amplifier concepts. The main goals were to achieve high gain (max. 100 dB) and to enable proper operation with NMOS-based THz detector. For the research needs three different architectures of chopper amplifier have been developed. The designed...
This paper summarizes work performed in ITE on development of ionizing radiation detectors integrated on-chip with readout electronics. First, the construction of such detectors will be presented in brief, together with the main features of non-typical silicon process deployed, then the test structures sent for prototyping will be discussed in detail.
This paper presents a dual stage charge-sensitive amplifier designed for long silicon strip detectors. It allows to obtain a linear Time-over-Threshold processing using constant current feedback for charge and interaction time measurements when working with large capacitance sensors (e.g. Cdet=30 pF). The paper includes details of architecture and simulation results.
This paper presents a hybrid fix point - floating point (FP) multiplication unit. It has as inputs a fixed point and a FP number and outputs a FP number. Algorithm and corresponding architecture are proposed. Two distinct approaches have been implemented on Xillinx Virtex 5 FPGA board: one geared towards performance whilst the second is optimized for cost. Synthesis results show an improvement up...
We report on the design and measurements of a prototype integrated circuit structure implemented in CMOS 180 nm technology and dedicated for readout of silicon pixel detectors. The prototype structure contains 16 channels, which are built of a charge sensitive amplifier and a main amplifier stage. We present both, the design procedure of the readout front-end electronics based on an inverter amplifier...
This paper presents the effect SOI detector's bias voltage has on current-voltage characteristics of different types of transistors (core transistors, io transistors, body floating, sourcetie, body-tie, low/normal/high threshold voltage). Methods of minimizing this effect were presented. Also, the I–V characteristic of transistors utilizing shielding layer (BPW - buried P Well) were measured and presented...
FATE is a project funded by the European Union under the program CIP/ICT-PSP with the main objective of organizing a big pilot on the automatic falls detection in aging people living at home. Automatic detection of falls is done in indoors and outdoors conditions, and in both cases the detection generates an alarm sent to a call center. The detection system is designed around a sensor sub-system based...
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