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The short-channel effect (SCE) is an important issue in CMOS technology. In this paper, a junctionless (JL) poly-Si nanowire FET (NW-FET) with gated raised source/drain (S/D) was demonstrated to suppress the SCE. The gated raised S/D structure enhances the control of the channel by the gate. Therefore, a JL poly-Si NW-FET with the gated raised S/D exhibits reduced drain-induced barrier lowering and...
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