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This paper presents a two-channel Hybrid Filter Bank (HFB) Analog-to-Digital Converter (ADC) that targets broadband digitization, for Cognitive Radio (CR) applications. The proposed architecture partitioning uses low-cost third order Butterworth analog filters and fourth order digital IIR filters. The optimization algorithm combines direct simplex search, minimax methods and a perturbation strategy...
A new method for the heuristic error estimation, based on nonuniform sampling, is presented. The error is defined as a maximal allowable change of the particular parameter implying small (preset) change of the objective function value. The method is suited to the sampling obtained from a genetic algorithm. The study case is shown. Application to Coulomb Excitation experiments (nuclear physics) data...
This paper presents how the optimization of continuous-time (CT) ΣΔ modulators by scaling the loop filter coefficients affects the signal transfer function (STF) and in which way the method can be used to reduce peaking in the STF. It is shown that, depending on the initial design, it is possible to define optimized parameter sets with increased performance and remaining flat STF or sets with constant...
Commonly used design procedures for design of digital differentiators are based on various optimization techniques and are also iterative in nature. The order estimation, for differentiators is important from design point of view as it can help in reducing the design time by providing a good initial guess of the order to the iterative design procedures. Moreover, order estimation helps in giving a...
In this paper, we propose a design method for a variable two-channel nonuniform-division FIR filter bank. The proposed filter bank can change the notch frequency in the stopband for each filter to reduce these noise. For changing notch frequencies, filter coefficients are approximated by polynomials using variable parameters in the proposed filter bank. In addition, the proposed filter bank satisfies...
Ever since the pioneering work of Y.C. Lim[1] on frequency response masking for the design of sharp FIR filters, lot of significant research have been carried out in this area. Among the various Signed Power of Two(SPT) forms, the Canonic Signed Digit(CSD) is a minimal representation, since it represents a given multiplier coefficient using minimum number of nonzero terms. This paper proposes the...
Automatic synthesis of analog circuits is being extensively studied and layout parasitics are increasingly being considered in the design loop. Layouts are built either through optimization or by instancing a template. In a circuit synthesis loop, the first approach is very expensive in terms of time complexity and the second one may lead low quality layouts. A better methodology will be to combine...
Pareto-optimal performance fronts have gained popularity as a representation of performance trade-offs of electronic circuits. They are also essential to support efficient bottom-up hierarchical design methodologies. Being such a key element in these methodologies, there have been many reported efforts to enhance the fronts with valuable information that goes beyond the nominal circuit behavior, such...
In this paper, symbolic matrices and a simple algebraic method to list spanning trees and find Hamiltonian circuits in a simple un-oriented graph are used. A concrete, fully-parallel algorithm that achieves both goals, with examples is shown. A necessary and sufficient condition for Hamiltonicity is presented, too.
Deep sub-micron CMOS technologies have enabled the development of highly digital radios for wireless communications at low Gigahertz frequencies [1], [2]. Meanwhile, nanometer scale CMOS allows to push the RF frequencies to the millimeter wave frequency range. Particularly 60GHz radio has emerged as the candidate for high-data-rate (10 Gb/sec), short-distance (1 to 10m) wireless communication systems...
This paper addresses the problem of optimizing gate-level area in a pipelined Multiple Constant Multiplications (MCM) operation and introduces a high-level synthesis algorithm, called HCUB-DC+ILP. In the HCUB-DC+ILP algorithm, initially, a solution with the fewest number of operations under a minimum delay constraint is found by the Hcub-DC algorithm. Then, the area around this local minimum point...
In this paper, the tapered-VTH methodology to design energy-efficient buffers in deep nanometer CMOS technology is deeply analyzed. Its effectiveness is demonstrated under various working conditions (variable final load, activity factor, supply voltage and process corner). Simulations based on a 45-nm technology showed that the tapered-VTH approach can provide a 3X energy reduction, at the parity...
This paper applies recently developed techniques for the PieceWise-Affine (PWA) approximation of explicit Model Predictive Control (MPC) to an Adaptive Cruise Control system. The optimal MPC law is approximated by using a particular class of PWA functions defined over a domain partitioned into simplices, referred to as PieceWise-Affine Simplicial functions. This approximation technique allows a very...
Very low frequency Gm-C filters are critical cells that should be carefully designed in order to avoid an excessive occupation of silicon area, especially when a high dynamic range is required. In this work we propose a routine, which exploits the MATLAB Optimization Toolbox in order to perform an optimum sizing of low frequency Gm-C integrators. The target is minimizing the integrator area, while...
The optimization of fixed coefficient FIR filter implementation has been focused mainly on the multiplier block where full precision fixed point arithmetic is normally used. Recently, an optimization method was proposed for the structural adders in FIR filters. This paper further proposes a method for gradually reducing the number of fractional bits within the structural adder block such that the...
In this paper a simple declarative language to define layout templates of analog circuits, named Layout Description Script (LDS), is introduced. In contrast to sequential description languages, coding constraints of a template is very easy with LDS. A methodology based on linear programming (LP) is presented to instantiate a layout from a set of LDS statements. Due to the LP formulation, area and...
This article presents maximisation of components tolerance together with finding optimal frequency of a periodic excitation in fault diagnosis of analogue electronic circuits. Addi-tionally classical two-stage “detection → location” diagnosis se-quence is merged into single step in order to reduce test time. Presented optimisation problems are solved by means of a ge-netic algorithm.
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