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Technology scaling is in the era where the chip performance is constrained by its power dissipation. Although the power limits vary with the application domain, they dictate the choice of technology, architecture, and implementation techniques that trade off performance for power savings. Energy-efficient design is often achieved for designs that are sensitive to technology and design parameters....
Software defined radios require selectable bandwidth digital filters to process the many different bandwidth signals pulled from or inserted into the ether. Implementation considerations favor fixed length digital filters with fixed coefficients that can be implemented with hardwired multipliers. This paper describes two filter architectures that use M-path polyphase partitions to implement variable...
In this paper, the design of variable fractional order differentiator (VFOD) using the infinite product expansion is presented. First, the infinite products of hyperbolic cosine and sine functions are applied to transform the VFOD design into the designs of first and second order digital log differentiators. Then, the FIR log differentiators designed by least-squares method are used to implement the...
This paper proposes a method to design low-delay fractional delay (FD) filters, using the Farrow structure. The proposed method employs both linear-phase and nonlinear-phase finite-length impulse response (FIR) subfilters. This is in contrast to conventional methods that utilize only nonlinear-phase FIR subfilters. Two design cases are considered. The first case uses nonlinear-phase FIR filters in...
Existing works on generating random bits by ring oscillators (ROs) mostly do not have detailed analysis on phase noise and jitter which are the entropy source of a random number generator. This paper analyzes the suitability of existing ROs for random number generation and possible improvements in order to increase the randomness of a RO. Randomness equations are derived, to understand efficiency...
This paper presents the design and functional simulation of a new multi-level bang-bang phase detector for use in a clock and data recovery circuit (CDR). The designed phase detector provides information of the nature of the delay between its input signals in a digitised manner, establishing six levels of quantisation. To avoid the metastability that hinders the performance of traditional bang-bang...
The effects of circuit non-idealities in a “Hogge ” -type phase detector are examined. Using a behavioral model for each circuit block, it is shown that various circuit non-idealities introduce static phase offset in the phase detector, reduce the monotonic range of its transfer characteristics and eventually degrade the capture range and jitter tolerance of the clock and data recovery (CDR) loop...
Analog Front End of any measurement devices suffer from the error arising out of the additive analog device offsets. Existing energy measurement device architectures uses a high pass filter (or a D.C. notch filter) at the output of the current channel Analog to Digital Converter (ADC) to cancel offsets generated by analog front-end, which makes it failing to measure the power consumption in a non-linear...
In this paper a phase compensation technique for the digital up conversion of a quadrature signal for amplification with switch mode power amplifiers is proposed. When a digital signal generator is used to generate the complex envelope signal care must be taken to compensate for the phase skew between the two paths. If phase compensation is not implemented an image caused by up converting the complex...
In this paper the practical aspects of the extracted window method applied to the nearly optimal fractional sample delay (FSD) filter design has been investigated. As the window method is one of the most numerically efficient digital filter design methods, this approach is well suited for variable fractional sample delay (VFSD) filter implementations which require frequent impulse response recalculation...
WiMAX (Worldwide Inter-operability for Microwave Access) is an emerging wireless technology standard, which enables high-speed packet data access. To anticipate future demands of WiMAX technology, we propose an all-digital phase-locked loop (ADPLL) based frequency synthesizer for the WiMAX RF transceiver. The developed ADPLL targets frequencies from 2.3–2.7 GHz and from 3.3–3.8 GHz for low band and...
This paper presents a new architecture for a overcurrent detection system, dedicated to fully integrated class-D audio amplifiers, that uses half the comparators than conventional architectures. A detailed implementation for a 1-W bridge-tied load (BTL) class-D amplifier, on a 0.18 µm CMOS technology is presented, showing a reduction of 28.8% in current consumption and 23.5% in silicon area, when...
Conditions for the existence of positive stable realizations with system Metzler matrices for proper transfer function are established. A method based on the decomposition of transfer functions into the first, second and third orders transfer functions for computation of positive stable realizations is proposed. A method for computation of positive stable realizations of transfer functions with real...
In this article, the main design tradeoffs in design of ultra-low-power (ULP) and robust digital systems will be discussed. Here, the goal is to explore the main tradeoffs among design parameters such as device sizes and supply voltage, and system parameters such as robustness and energy dissipation. This study provides the necessary basis for design optimization and comparing the conventional CMOS...
Today's multi-media electronic era is driven by the increasing demand for small multifunctional devices able to support diverse services. Unfortunately, the high levels of transistor integration and performance required by such devices lead to an unprecedented increase of on-chip power that significantly limits the battery lifetime and even poses reliability concerns. Several techniques have been...
Various synthesis strategies relying on conventional standard-cell libraries (SCLs) are evaluated in order to minimize the energy dissipation per operation in sub-threshold (sub-VT) systems. First, two sub-VT analysis methods are reviewed, both of which allow to evaluate the energy dissipation and performance in the sub-VT regime for designs which have been synthesized using a 65-nm CMOS SCL, characterized...
The concept of high-order ramp analog-to-digital converter and its design aiming at medium-high resolution (12–14 bits) are presented. Design methods that give rise to various Nyquist rate schemes resembling incremental converters are described. Since for Nyquist rate achieving noise shaping is not the goal, the design care is just maintaining good stability to avoid performance degradation. Different...
This paper addresses the problem of optimizing gate-level area in a pipelined Multiple Constant Multiplications (MCM) operation and introduces a high-level synthesis algorithm, called HCUB-DC+ILP. In the HCUB-DC+ILP algorithm, initially, a solution with the fewest number of operations under a minimum delay constraint is found by the Hcub-DC algorithm. Then, the area around this local minimum point...
In this paper, the tapered-VTH methodology to design energy-efficient buffers in deep nanometer CMOS technology is deeply analyzed. Its effectiveness is demonstrated under various working conditions (variable final load, activity factor, supply voltage and process corner). Simulations based on a 45-nm technology showed that the tapered-VTH approach can provide a 3X energy reduction, at the parity...
This paper proposes high performance dedicated hardware architecture for the Haar Wavelet transform, whose structure is based on nine levels of decomposition. The architecture is described in hardware description language VHDL, and it has been designed by using fixed point arithmetic, and also using efficient arithmetic operators into their sub modules. The efficiency of the architecture was proved...
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