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A high speed comparator based on a high DC-gain folded-cascode amplifier is presented. Four switches rearrange the structure to speed up the comparison process and prevent kickback noise with a simple set of controlling signals. The circuit is a rail-to-rail folded-cascode amplifier during reset/evaluation period which transforms into two back-to-back inverters during the latch period to speed up...
This paper presents the design and functional simulation of a new multi-level bang-bang phase detector for use in a clock and data recovery circuit (CDR). The designed phase detector provides information of the nature of the delay between its input signals in a digitised manner, establishing six levels of quantisation. To avoid the metastability that hinders the performance of traditional bang-bang...
The effects of circuit non-idealities in a “Hogge ” -type phase detector are examined. Using a behavioral model for each circuit block, it is shown that various circuit non-idealities introduce static phase offset in the phase detector, reduce the monotonic range of its transfer characteristics and eventually degrade the capture range and jitter tolerance of the clock and data recovery (CDR) loop...
In this paper, the N-phase current driven passive mixer clocked by 1/N duty-cycle clocks is analyzed. The analysis shows that the N-phase passive mixer holds the property of impedance transformation, where it can frequency-translate baseband lowpass impedances into RF frequency to synthesize high-Q bandpass filters. This property can be used to replace the off-chip SAW filter in wireless receivers...
A Continuous-Time Sigma-Delta (ΣΔ) Modulator for Bluetooth with 52MHz sampling frequency in a 1.2V 65nm CMOS process is presented. The modulator has a proposed single-stage 3rd-order 4-bit architecture, which employs a dual-loop feedback method to compensate the loop delay up to one clock period. A 4-bit flash ADC and a 4-bit current-steering DAC are used to improve the resolution and stability. Non-Return-Zero...
WiMAX (Worldwide Inter-operability for Microwave Access) is an emerging wireless technology standard, which enables high-speed packet data access. To anticipate future demands of WiMAX technology, we propose an all-digital phase-locked loop (ADPLL) based frequency synthesizer for the WiMAX RF transceiver. The developed ADPLL targets frequencies from 2.3–2.7 GHz and from 3.3–3.8 GHz for low band and...
This paper presents a new architecture for a overcurrent detection system, dedicated to fully integrated class-D audio amplifiers, that uses half the comparators than conventional architectures. A detailed implementation for a 1-W bridge-tied load (BTL) class-D amplifier, on a 0.18 µm CMOS technology is presented, showing a reduction of 28.8% in current consumption and 23.5% in silicon area, when...
In this paper, the use of the SB-ZePoC Coding-Scheme for a high precision AC Power-Standard (TET-Watt) is proposed. The use of SB-ZePoC allows a novel approach to binary switched precision-sources, as the switching-rate is low compared to sigma-delta modulation. The structure of the system allows to reference the output amplitude directly to a DC-voltage-reference or switching a binary source directly...
A new cyclic ADC structure achieving capacitor mismatch insensitivity is presented. This technique enables cyclic ADC to obtain a very precise residue voltage in cycles independent of matching of capacitors. In addition, this new structure saves the die area of capacitors in the switched capacitor network by 25% and significantly reduces power consumption by up to 40%. A 12-bit 1.67MS/s cyclic ADC...
An event-driven, clock-free analog-to-digital converter (ADC) based on a continuous-time delta modulation technique is presented in this work. The ADC output is a digital datum, continuous in time. The ADC system employs an unbuffered, area efficient segmented resistor-string digital-to-analog converter (DAC). Simulation results of the high level model of an 8-bit event-driven DM ADC system is presented...
The effect of nonlinearities in injection-locked frequency dividers is investigated and it is shown that the presence of nonlinearities, such as in a CML DFF-based divider, results in a wider frequency locking range. A new divider topology is presented that exhibits both higher operating frequencies and similar wide-locking range compared to the conventional CML DFF-based topology. The chip was fabricated...
Today's multi-media electronic era is driven by the increasing demand for small multifunctional devices able to support diverse services. Unfortunately, the high levels of transistor integration and performance required by such devices lead to an unprecedented increase of on-chip power that significantly limits the battery lifetime and even poses reliability concerns. Several techniques have been...
Various synthesis strategies relying on conventional standard-cell libraries (SCLs) are evaluated in order to minimize the energy dissipation per operation in sub-threshold (sub-VT) systems. First, two sub-VT analysis methods are reviewed, both of which allow to evaluate the energy dissipation and performance in the sub-VT regime for designs which have been synthesized using a 65-nm CMOS SCL, characterized...
In this paper a 10-bit, 5kHz bandwidth, continuous time ADC, which employs level-crossing sampling to convert an analog signal to a digital one, is presented. The proposed level-crossing ADC does not use any clock and sampling in time is not involved. The level-crossing ADC acquires samples only when they provide a new information about the input signal, thus dissipating power only when needed. Cadence...
This paper proposes high performance dedicated hardware architecture for the Haar Wavelet transform, whose structure is based on nine levels of decomposition. The architecture is described in hardware description language VHDL, and it has been designed by using fixed point arithmetic, and also using efficient arithmetic operators into their sub modules. The efficiency of the architecture was proved...
Galois field arithmetic circuits find wide variety of application in cryptography. Thus they faces majority of the hardware based attacks for malicious gain. Though there are many approaches that have been proposed to mitigate such malicious attacks, most of them are inappropriate for practical applicability due to various design drawbacks. It is noted that Galois field multipliers are one among the...
This paper proposes a new Built-In Self Test architecture to detect time interval errors (TIE) of Phase-Locked Loops. A transient current sensor utilizing Flipped Voltage Follower (FVF) is used with a comparison block in the proposed topology. It is designed and verified for IBM 65nm technology using 1 V supply voltage and capable of detecting both steady-state and transient currents up to 150 µA...
This paper addresses the problem of the stability and the performance analysis of N-nodes cartesian networks of self-sampled all digital phase-locked loops. It can be demonstrated that under certain conditions (such as proper filter coefficient values), a global and a local synchronization can be obtained. Our approach to find the optimal conditions consists of analyzing a corresponding linear average...
This article presents the optimization process for a new architecture of digital-enhanced radio frequency receiver. This receiver is based on combining charge sampling filters and hybrid filter banks techniques. We describe the structure optimization based on a compromise between performance and implementation constraints. We then show the performances evaluation in system-level and electrical level...
This paper employs a CMOS 0.18 µm CMOS technology to design a 6-bit 250 MS/s pipelined ADC with open-loop amplifiers. The amplifiers utilize MOS transistors in triode region instead of resistors and current sources to decrease the process variation and the need of bias circuits. The amplification managed with the global-gain-control loop which realizes the error amplifier with a comparator in low-bandwidth...
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