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This paper presents a new processor array architecture for scalable radix 8 Montgomery modular multiplication algorithm. In this architecture, the multiplicand and the modulus words are allocated to each processing element rather than pipelined between the processing elements as in the previous architectures extracted by G. Todorov. Moreover, the multiplier bits are fed serially to the first processing...
In this paper, we present the acceleration of a pre-trained feedforward artificial neural network executing on a NIOS II processor. Without the use of hardware acceleration, a feedforward artificial neural network spends much of its execution time on the calculation of the activation function between layers, in this case, the hyperbolic tangent function. A speedup of 4.36 was achieved via a custom...
High performance implementation of 2D digital filters are highly desired in many applications for real-time processing. In this paper, a multiprocessor realization of a 2D denominator separable digital filter is implemented in Altera Stratix III FPGA. The implementation achieves a data throughput equivalent to one multiplication and two additions, plus one clock cycle. It has been found that the maximum...
This paper presents a performance-optimized version of the flexible triangle (FTS) block-matching search algorithm. The FTS is a fast block-matching algorithm for motion estimation proposed in previous work that, given a block of pixels, is used to search for the best-matching block in a given search area using only a selected subset of available positions rather than searching all available positions...
One of the issues of power amplifier used in satellite communications is its nonlinearity. Digital predistortion is used in a linearizer to inverse this undesired effect to achieve higher efficiency to the amplifier. Xilinx provides a predistortion core to be implemented in FPGA devices. The core is used in a linearizer to test its functionality and performance. Simulation results indicate a gain...
Catastrophe events can happen when a computer or a computer network is exposed to the Internet without any security protection. The security issues can be mitigated by setting up a firewall between the inside network and the outside world. This paper describes a design of a highly customizable hardware packet filtering firewall to be embedded on a network gateway. A packet filtering firewall controls...
Dense stereo disparity map provides a robust method on distance measurements in a 3D scene. Due to its computational complexity in nature, it has been a challenge to achieve real-time processing. In the past years, various algorithms have been studied in order to reach the goal of real-time processing. In this paper, a Dynamic Time Warp (DTW) algorithm is proposed. The DTW algorithm provides excellent...
Independent component analysis (ICA) is an important signal processing technique used to extract source signals from signal mixtures. Although useful in a wide range of problems, ICA is computationally expensive, and is therefore not suitable in many real-time or large data size applications. This paper presents a scalable parallel implementation of ICA in which computations are performed on graphics...
The current trend of digital convergence leads to the need of the video decoder that should support multiple video standards such as, H.264/AVC, JPEG, MPEG-2, VC-1, and AVS on a single platform. In this paper, we present a resource-shared architecture of multiple transforms to support all five video codecs. The architecture is based on a new multi-dimensional delta mapping. Here the Inverse Discrete...
In real time applications or portable devices, software implementation is not enough by itself to evaluate a signal feature analysis technique and a hardware implementation needs to be considered. The selection of the right signal feature analysis technique for an application depends on the algorithmic (software) performance, and also on the hardware efficiency of that technique. However, there are...
This paper describes parallelization of the JasPer reference software for JPEG-2000 and presents results from simulation, and from hardware execution on a multicore processor where speedups of more than 2 are obtained with 4 processors. Loop fusion is applied before parallelization to increase workload granularity. Results from profiling and cache behavior analysis are presented to establish the expected...
We present the Digital Dash Reconfigurable Tactile Display (RTD), a projection-based multi-touch centre stack replacement for automobiles. After reviewing the system architecture, we detail the software challenges faced when developing touch screen software with limited computational resources.
In this paper, we propose a simplified Log-MAP algorithm that is equivalent to the Log-MAP algorithm in terms of the bit-error-rate (BER) performance, but without its implementation difficulties. The proposed algorithm is based on a linear approximation of the correction function in the Log-MAP algorithm over different signal-to-noise ratio (SNR) regions. This approximation is simple to implement...
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