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Low supply voltage is a commonly method for suppressing system power consumption and thermal effects, improving battery life and chip reliability for mobile SoC and 3D-IC devices. This paper describes various mainstream and emerging embedded non-volatile memory (eNVM) solutions for mobile SoC and 3D-IC designs. This study also reviews and discusses the key circuit technologies for decreasing the VDDmin...
This paper presents a mobile security SoC to deal with intensive cryptography algorithms for different security protocols. A MIPS-like general processor, a dedicated package processor for fast data package, and multiple security processors for cryptography are integrated in the SoC. Moreover, the performance can be greatly enhanced by the well-designed DTU (Data Transfer Unit), memory architecture...
The open-loop de-skewing circuits are traditionally used for fast clock synchronization, but they are unable to deal with the problems induced by run-time variations. This paper presents the design of a skew compensation circuit that can achieve fast lock-in and also perform maintenance operation after lock-in. This circuit is designed on top of the open-loop half-delay-line skew compensation circuit...
A novel Boundary-Scan circuit compatible with IEEE 1149.1 standard and designed for our SOI-Based FPGA is presented in this paper. The new Boundary-Scan circuit serves the test of FPGA at the chip as well as board level and the added features facilitate the configuration and verification functions of FPGA. The Boundary-Scan circuit in this paper has been implemented in an SRAM-Based FPGA fabricated...
With the number of processor cores increasing in chip multi-processors (CMPs) and global wire delays increasing, networks on chip have been gaining wide acceptance for on-chip inter-core communication. This paper introduces a low latency Dynamic Virtual Output Queues Router (DVOQR), which can reduce the router latency to two cycles by leveraging look-ahead routing computation and virtual output address...
In this paper, we propose an efficient approach to reduce the effect of the Simultaneous Switching Noise (SSN) for mixed System on Chip (SoC). In order to validate the approach, we have designed a 14-bits 100MHz pipeline ADC as an example. Finite Element Method (FEM) and Method of Moment (MoM) are chose to do the electromagnetic extraction of package and bond-wires separately. The proposed approach...
This paper accesses the main factors that affect the resonant frequency and power consumption in on-chip transformer based bufferless resonant clock distribution network(CDN), such as on-chip transformers with different ratio, wire width of clock grid and the size of energy compensating cell. Through an unsigned 32*32 bit pipeline multiplier under TSMC 65nm CMOS technology, we perform a post-layout...
In this paper, a high-accuracy CMOS on-chip RC oscillator (OSC) for MCU application is presented. The oscillator can provide a 16 MHz output frequency with the total accuracy in ±1% in all process corner at 1.8 v and 55°C condition, ±2% in all process, supply voltage and temperature condition after 7bit digital trimming. This design features low sensitivity to power supply from 1.8 v to 6.0 v and...
A 2.4GHz receiver front-end with on-chip balun implemented with 0.13um CMOS technology is presented in this paper. Based on direct-conversion architecture, the front-end comprises a two-stage LNA (low noise amplifier) with optimized on-chip transformer and quadrature passive mixer. The gm-boosting technique is employed in 1st stage of LNA to achieve low noise and low current simultaneously. In 2nd...
In the design of a SOC system, random test is gradually becoming an application for IP cores verification. This paper proposes a new random testing circuit based on LFSR to test the integrated EMIF IP core with restricted random verification methods. With the pseudo-random numbers generated by LFSR which works as a pseudo-random number generator, the testing circuit converts the numbers into test...
22nm node Si SOI Coplanar “N Channel Vertical Dual Carrier Field Effect Transistors” (VDCFET) and its SOC with effective channel length less than 10nm for communication applications are presented.
Silicon-controlled rectifier (SCR) had been reported with good electrostatic discharge (ESD) robustness and low parasitic capacitance. In this work, SCR devices were investigated to have low and constant capacitance for on-chip ESD protection in RF ICs. The test devices had been verified in a 65-nm fully-silicided CMOS process. The SCR devices can pass 8-kV human-body-model (HBM) ESD tests, and the...
A fully differential common-source cascode low noise amplifier(LNA) is presented for wireless receivers. The capacitive cross-coupling technique combined with cascode transistor is introduced to enhance LNA gain and reduce noise figure as well as the nonlinearity influence of cascaded transistors. A 2.6 mm long on-chip folded dipole antenna is integrated with this LNA and co-design is performed for...
Increasing complexity and manufacturing costs, along with the fundamental limits of planar CMOS devices, threaten to slow down the historical pace of progress in the semiconductor industry. We report herein an efficient, low-cost, "greener" way to fabricate dual-damascene copper (Cu) on-chip interconnect or Back-End-Of-the-Line (BEOL) structures using a novel multifunctional on-chip insulator,...
Because of the special p-i-n structure of the tunneling FET (TFET), many different composite transistors can be formed with careful device design by combining TFET with MOSFET. In this paper, we propose the special applications of TFET as memory devices. A novel capacitor-less DRAM cell based on floating junction gate (FJG) concept can be configured with TFET. In addition, several different memory...
In this work, a low noise and low power charge sensitive preamplifier (CSA) based on CSMC 0.6 μm double poly mix CMOS technology was designed and simulated. In this design, two MOSFETs were used as a feedback resistor and a feedback capacitor respectively to replace an on-chip resistor in parallel and an on-chip capacitor in a conventional CSA. Simulation results show that this design can reduce the...
A new on-chip CR-based electrostatic discharge (ESD) detection circuit for system-level ESD protection design is proposed in this work. The circuit performance to detect positive or negative electrical transients generated by system-level ESD tests has been analyzed in HSPICE simulation and verified in silicon chip. The experimental results in a 0.13-μm CMOS process have confirmed that the proposed...
Today the research on design for testability is becoming the research priority in the filed of SoC. However, the traditional research is limited in top level of SoC and it ignores the inference resulting from the scheduling strategy in IP-core level. In addition, the work on stage of SoC overly focuses on researching the minimum testing time of different WSC. It ignores the relationship between the...
This paper presents a method of multi-Scan-Enable DFT design for at-speed scan testing to improve transition fault coverage. Base on the method, we build a novel TR-TC (Test Resources-Test Coverage) associated test cost mathematical model to effectively control the complexity of at-speed DFT design and establish the optimization number of Scan-Enable, which provides a reliable target control value...
High speed, low power and compatibility with standard technology Static random access memory (SRAM) is essential for system on chip (SoC) technology. In this paper, we first present a 6T-SRAM (1WR) and two types of 8T-SRAM cell(2WR 1W1R). After that how the (1W1R) cell work with external unit is explained, and we compare the SNM sensitivity and the write/read operations time of 1WR 1W1R cell.
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