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So far the most aggressive manufacturing forecast for 22nm technology node is in late 2011, and there still remains many arguments for its next generation, 15nm manufacturing technologies. The major obstacles in front of the manufacturing are (1) high cost fine patterning technology, (2) tradeoff of SRAM cell size and performance, (3) increasing variability, (4) short channel effect control, etc....
This work presents a preliminary performance comparison between the new and conventional block oxide (BO) bulk-MOSFETs that suggests the proposed BO structure as a candidate for scaling planar CMOS to 16 nm generation and beyond. Also, the combined application of the isolation-last process (ILP) and the BO process provides a method of forming a new BO (NBO) structure that diminishes the short-channel...
An analytical model for high voltage Thin-film Silicon-On-Insulator (TSOI) lateral devices is proposed in this paper. A new Reduced SURface Field (RESURF) criterion is obtained for TSOI lateral devices with a lateral linear doping in the drift region. The optimum drift doping profile for TSOI lateral devices can be obtained from the new RESURF criterion. The analytical results are in good agreement...
In this paper, a preparation process of PCRAM access-diode-array with proprietary intellectual property rights (PIPR) is shown simply. Then, Relationship between device parameters and diode performance, including drive-current, breakdown, especially disturb-current, which influences the data-veracity and reliability of PCRAM, is analyzed from the views of carriers distribution and parasitic PNP-BJT...
In this paper, the impacts of diameter-dependent annealing (DDA) effect on nanowire S/D extension random dopant fluctuations (SDE-RDF) in silicon nanowire MOSFETs (SNWTs) are investigated, in terms of electrostatic properties, source/drain series resistance (RSD), and driving current. The SDE-RDF induced variations of threshold voltage (Vth) and DIBL in SNWTs with different diameters are found to...
In this paper, the forward gated-diode method is used to extract the gate oxide thickness and doping concentration of MOS device simultaneously. The gate oxide thickness and body doping concentration are first extracted from the recombination-generation (R-G) current, and then from the simulation result of ISE-Dessis. The results obtained from R-G method shows a good agreement with the simulation...
This paper presents the characteristics of ideal double-gate/gate-all-around (DG/GAA) MOSFETs, including the long/short-channel and thin/thick-body effects. A unified compact model (Xsim) based on the unified regional modeling (URM) approach for the generic DG/GAA MOSFET is used to demonstrate the expected behaviors, which should be included in the core model describing such emerging devices.
This paper gives a brief overview on recent advances in bipolar junction transistor (BJT) modeling and related simulation applications in circuit design. This work starts with a review of existing BJT compact model formulations, and covers a broad range of advanced topics such as precision temperature modeling, sub-circuit design, mismatch and corner modeling, and BJT scalable model.
According to 2009 ITRS roadmap, advances in process technologies, introduction of new materials, and adoption of new device architectures are expected to enable CMOS scaling to 22nm node and beyond. The added process complexity will likely to lead to increased process development time and cost. Predictive TCAD modeling can be invaluable to guide development direction, narrow down experimental conditions...
In this paper, a short-channel subthreshold swing model for three-terminal (3T) double-gate (DG) MOSFETs with Gaussian doping profile in the vertical direction of the channel is presented. The effective conduction path effect concept of uniformly doped DG MOSFETs is utilized to incorporate the doping dependency in the present model. The effect of varying peak doping position of Gaussian profile on...
PIN tunneling field effect transistor (TFET) is one of the most promising devices due to its low sub-threshold swing. In this paper, using TCAD simulation, we investigate the doping and structure dependence of the electric field in PIN TFET. We show that an insertion of a thin N layer into PIN structure (i.e., PNIN TFET) not only enhances the drive current but also improves the reliability of the...
The dependence of the avalanche breakdown voltage on vertically linear doping gradient of the drift region based on Silicon-On-Insulator (SOI) lateral diffuse metal oxide semiconductor (LDMOS) is studied. Vertically linear doping profile (VD) of the LDMOS structure is exhibited to obviously improve safe of operation area (SOA) from the conventional uniform and variable linear doping structure. From...
An ion vertical striking on SOI CMOS transistor sensitive region creates an obvious large current resulting in upset of output node. Since parasitic BJT act, the single-event effect (SEE) is enhanced. In order to evaluate this effects, it is desirable to calculate critical charge (Qcrit, charge collected by the drain during the entire SEE) and the duration of output voltage pulse. With ISE TCAD, two-dimensional...
A 2D analytical model of the bulk-silicon triple RESURF devices is proposed. Based on the 2D Poisson's solution, the new analytical expressions of the surface potential and electric field distributions are obtained. According to the model and the semiconductor device simulator Medici, the electric field reduction mechanism and breakdown characteristics in the device are discussed. Further, a RESURF...
The terahertz frequency GaN Gunn diodes with GaN and AlGaN electron launchers are investigated by using an improved NDM model of GaN. The simulations demonstrate that there exists a shift of the oscillation mode from dipole domain mode toward accumulation mode with increased temperature, and the AlGaN launcher GaN Gunn diode can generate better power performance at stable oscillation mode than the...
In this paper a potential based model for monocrystalline silicon thin film transistor (TFT) systems on glass (SOG) substrate from the accumulation to the strong-inversion region is developed. By solving the complete dimensional (1D) Poisson's equation, the potential distribution in the channel is obtained. The analytic drain current is expressed accurately base on the potential solution. Compared...
The dual-material gate and asymmetrical halo structure is used in surrounding gate MOSFET to improve the performance. By treating the device as three surrounding-gate MOSFETs connecting in series and maintaining current continuity, a comprehensive drain current model is developed for it. It is concluded that the device also exhibits increased current drivability and improved hot carrier reliability...
A vertical pnp BJTs on thin SOI is designed and characterized by using the mixed numerical two-dimensional process and device simulator (Sentaurus). The DC, frequency, and breakdown characteristics of the vertical pnp on SOI are simulated and analyzed. The peak of β is 85 at Vbe=-0.7. The maximum of the cutoff frequency fτ for the pnp bipolar transistor on SOI attain 10.6 GHz, and the value of BVceo...
An improved mobility model for device simulation is presented. The model is based on charge density instead of effective surface electric field. Compared to the other models, it accounts for substrate bias effect and channel length dependence.
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